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ADS130E08 Datasheet(PDF) 7 Page - Texas Instruments |
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ADS130E08 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 56 page DAISY_IN DOUT SCLK MSB t DISCK2ST MSB 2 1 3 n n+1 n+2 MSB LSB t DISCK2HT t DOST 0 LSB n+3 1 CS CLK DIN DOUT 2 3 8 1 2 8 3 t CSSC t DIST t DIHD t DOHD t CSH t DOST t SCLK t SPWH t SPWL t SDECODE t SCCS Hi-Z t CSDOZ t CSDOD Hi-Z t CLK SCLK ADS131E04 ADS131E06 ADS131E08 www.ti.com SBAS561 – JUNE 2012 TIMING CHARACTERISTICS NOTE: SPI settings are CPOL = 0 and CPHA = 1. Figure 1. Serial Interface Timing (1) n = Number of channels × resolution + 24 bits. Number of channels is 4, 6, or 8; resolution is 16-bit or 24-bit. Figure 2. Daisy-Chain Interface Timing Timing Requirements For Figure 1 and Figure 2(1) 2.7 V ≤ DVDD ≤ 3.6 V 1.7 V ≤ DVDD ≤ 2.0 V PARAMETER DESCRIPTION MIN MAX MIN MAX UNIT tCLK Master clock period 444 588 444 588 ns tCSSC CS low to first SCLK: setup time 6 17 ns tSCLK SCLK period 50 66.6 ns tSPWH, L SCLK pulse width, high and low 15 25 ns tDIST DIN valid to SCLK falling edge: setup time 10 10 ns tDIHD Valid DIN after SCLK falling edge: hold time 10 11 ns tDOHD SCLK falling edge to invalid DOUT: hold time 10 10 ns tDOST SCLK rising edge to DOUT valid: setup time 17 32 ns tCSH CS high pulse 2 2 tCLKs tCSDOD CS low to DOUT driven 10 20 ns tSCCS Eighth SCLK falling edge to CS high 4 4 tCLKs tSDECODE Command decode time 4 4 tCLKs tCSDOZ CS high to DOUT Hi-Z 10 20 ns tDISCK2ST Valid DAISY_IN to SCLK rising edge: setup time 10 10 ns tDISCK2HT Valid DAISY_IN after SCLK rising edge: hold time 10 10 ns (1) Specifications apply from –40°C to +105°C, unless otherwise noted. Load on DOUT = 20 pF || 100 k Ω. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): ADS131E04 ADS131E06 ADS131E08 |
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