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DLPR100DWC Datasheet(PDF) 1 Page - Texas Instruments

No. de pieza DLPR100DWC
Descripción Electrónicos  DLP짰 Configuration PROM for DLPC100
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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DLPR100DWC Datasheet(HTML) 1 Page - Texas Instruments

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CS
DO
WP
GND
1
2
3
4
8
7
6
5
HOLD
DIO
CLK
V
CC
DLPR100
www.ti.com
DLPS020 – DECEMBER 2009
DLP® Configuration PROM for DLPC100
Check for Samples: DLPR100
1
FEATURES
Programmed for Use With the DLPC100 and DLP1700 (0.17 HVGA Chipset)
Data Transfer up to 150 M-Bits/Second
Single 2.7 to 3.6 V Supply
5 mA Active-Current, 1-
μA Powerdown (Typ)
–40°C to 85°C Operating Temperature Range
DESCRIPTION
The DLPR100 is one of three components in the 0.17 HVGA chipset (see Block Diagram). Proper function and
operation of the DLPR100 requires that it be used in conjunction with the other components of the 0.17 HVGA
chipset. Refer to the 0.17 HVGA Chip-Set data sheet for further details (TI Literature Number DLPS017).
The serial flash device provides a storage solution for the DLPC100 device in the 0.17 HVGA chipset. The
device operates on a single 2.7 V to 3.6 V power supply with current consumption as low as 5 mA active and 1
µA for power-down. The DLPR100 supports the standard Serial Peripheral Interface (SPI). SPI clock frequencies
of up to 75 MHz are supported.
ORDERING INFORMATION
TA
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–40°C to 85°C
DLPR100DWC
By Pin 1
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NO.
NAME
Chip select, active low. When CS is high, the device is deselected and DO pin is high
1
CS
I
impedance.
2
DO
O
Data output. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
Write protect input, active low. Disables writes to the status register when the Status Register
3
WP
I
Protect (SRP) bit is set to a 1 state.
4
GND
Ground
5
DIO
I/O
Data input/output. Data is latched on the rising edge of the CLK input pin.
6
CLK
I
Serial clock. Provides the timing clock for the serial input and output operation.
Hold input, active low. Allows the device to be paused. When HOLD is brought low, while CS
7
HOLD
I
is low, the DO pin will be at high impedance and signals on the DIO and CLK pins will be
ignored. Device operation will resume when HOLD is brought high.
8
VCC
Power supply
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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