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SN74SSTEB32866 Datasheet(PDF) 15 Page - Texas Instruments |
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SN74SSTEB32866 Datasheet(HTML) 15 Page - Texas Instruments |
15 / 37 page ELECTRICAL CHARACTERISTICS SN74SSTEB32866 www.ti.com..................................................................................................................................................................................................... SCAS851 – APRIL 2009 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP( MAX UNIT 1) IOH = –100 µA 1.7V to 1.9V VCC–0.2 IOH = –6 mA 1.7V 1.3 VOH Q outputs, PPO V IOH = –100 µA 1.425V to VCC–0.2 1.575V IOH = –6 mA 1.425V 1.0 IOL = 100 µA 1.7V to 1.9V 0.2 IOL = 6 mA 1.7V 0.4 Q outputs, PPO 1.425V to IOL = 100 µA 0.2 1.575V VOL V IOL = 6 mA 1.425V 0.4 IOL = 25 mA 1.7V 0.5 QERR output IOL = 25 mA 1.425V 0.5 VI = GND -5 PAR_IN II VI = VCC 1.9V 25 µA All other inputs(2) VI = VCC or GND ±5 IOZ QERR output VO = VCC or GND 1.9V ±10 µA Static standby RESET = GND 200 µA ICC IO = 0 1.9V Static operating RESET = VCC, VI = VIH(AC) or VIL(AC) 40 mA RESET = VCC, VI = VIH(AC) or VIL(AC), Dynamic operating – clock CLK and CLK switching 50% duty 45 µA/MHz only cycle Dynamic operating – per RESET = VCC, VI = VIH(AC) or VIL(AC), ICCD each data input, 1:1 IO = 0 1.8V 43 CLK and CLK switching 50% duty µA clock configuration cycle, one data input switching at MHz/D Dynamic operating – per one-half clock frequency, 50% duty input each data input, 1:2 60 cycle configuration Chip-select-enabled RESET = VCC, VI = VIH(AC) or VIL(AC), low-power active mode – CLK and CLK switching 50% duty 45 µA/MHz clock only cycle Chip-select-enabled ICCDL RESET = VCC, VI = VIH(AC) or VIL(AC), low-power active mode - IO = 0 1.8V 2 P CLK and CLK switching 50% duty µA clock 1:1 configuration cycle, one data input switching at MHz/D Chip-select-enabled one-half clock frequency, 50% duty input low-power active mode – 3 cycle 1:2 configuration Data inputs, CSR, PAR_IN VI = VREF ± 250 mV 1.8V 2.5 3 3.5 CI CLK, CLK VICR = 0.9 V, VI(PP) = 600 mV 2 3 pF RESET VI = VCC or GND 4 (1) All typical values are at VCC = 1.8 V, TA = 25°C. (2) Each VREF pin (A3 or T3) should be tested independently, with the other (untested) pin open. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Link(s): SN74SSTEB32866 |
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