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SMOMAPL138B-HIREL Datasheet(PDF) 1 Page - Texas Instruments |
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SMOMAPL138B-HIREL Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 282 page  SMOMAPL138B-HiRel www.ti.com SLVSAQ9A – JANUARY 2011 – REVISED JANUARY 2012 SMOMAPL138B Low-Power Applications Processor Check for Samples: SMOMAPL138B-HiRel 1 SMOMAPL138B Low-Power Applications Processor 1.1 Features 123 – Normalization, Saturation, Bit-Counting • Highlights – Compact 16-Bit Instructions – Dual Core SoC • C674x Two Level Cache Memory Architecture • 375/456-MHz ARM926EJ-S ™ RISC MPU – 32K-Byte L1P Program RAM/Cache • 375/456-MHz C674x Fixed/Floating-Point VLIW DSP – 32K-Byte L1D Data RAM/Cache – Enhanced Direct-Memory-Access Controller – 256K-Byte L2 Unified Mapped RAM/Cache (EDMA3) – Flexible RAM/Cache Partition (L1 and L2) – Serial ATA (SATA) Controller • Enhanced Direct-Memory-Access Controller 3 – DDR2/Mobile DDR Memory Controller (EDMA3): – Two Multimedia Card (MMC)/Secure Digital – 2 Channel Controllers (SD) Card Interface – 3 Transfer Controllers – LCD Controller – 64 Independent DMA Channels – Video Port Interface (VPIF) – 16 Quick DMA Channels – 10/100 Mb/s Ethernet MAC (EMAC): – Programmable Transfer Burst Size – Programmable Real-Time Unit Subsystem • TMS320C674x Floating-Point VLIW DSP Core – Three Configurable UART Modules – Load-Store Architecture With Non-Aligned – USB 1.1 OHCI (Host) With Integrated PHY Support – USB 2.0 OTG Port With Integrated PHY – 64 General-Purpose Registers (32 Bit) – One Multichannel Audio Serial Port – Six ALU (32-/40-Bit) Functional Units – Two Multichannel Buffered Serial Ports • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double • Dual Core SoC Precision/64-Bit) Floating Point – 375/456-MHz ARM926EJ-S™ RISC MPU • Supports up to Four SP Additions Per – 375/456-MHz C674x VLIW DSP Clock, Four DP Additions Every 2 Clocks • ARM926EJ-S Core • Supports up to Two Floating Point (SP or – 32-Bit and 16-Bit (Thumb®) Instructions DP) Reciprocal Approximation (RCPxP) – DSP Instruction Extensions and Square-Root Reciprocal – Single Cycle MAC Approximation (RSQRxP) Operations Per – ARM® Jazelle® Technology Cycle – EmbeddedICE-RT™ for Real-Time Debug – Two Multiply Functional Units • ARM9 Memory Architecture • Mixed-Precision IEEE Floating Point Multiply Supported up to: – 16K-Byte Instruction Cache – 2 SP x SP -> SP Per Clock – 16K-Byte Data Cache – 2 SP x SP -> DP Every Two Clocks – 8K-Byte RAM (Vector Table) – 2 SP x DP -> DP Every Three Clocks – 64K-Byte ROM – 2 DP x DP -> DP Every Four Clocks • C674x Instruction Set Features • Fixed Point Multiply Supports Two 32 x – Superset of the C67x+™ and C64x+™ ISAs 32-Bit Multiplies, Four 16 x 16-Bit – Up to 3648/2746 C674x MIPS/MFLOPS Multiplies, or Eight 8 x 8-Bit Multiplies per – Byte-Addressable (8-/16-/32-/64-Bit Data) Clock Cycle, and Complex Multiples – 8-Bit Overflow Protection – Instruction Packing Reduces Code Size – Bit-Field Extract, Set, Clear – All Instructions Conditional 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 TMS320C6000, C6000 are trademarks of Texas Instruments. 3 ARM926EJ-S is a trademark of ARM Limited. PRODUCTION DATA information is current as of publication date. Products conform to Copyright © 2011–2012, Texas Instruments Incorporated specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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