I

OS

I

OS

I

OC

V

IN

V

IN

I

OUT

I

OUT

Decreasing

Load

Resistance

Decreasing

Load

Resistance

Flat Current Limit

Current Limit with Peaking

0 A

0 A

0 V

0 V

Slope = –R

DS(on)

Slope = –R

DS(on)

TPS2530

SLUSB67 – AUGUST 2012

www.ti.com

There are two kinds of current limit profiles typically available in TI switch products similar to the TPS2530. Many

older designs have an output I vs V characteristic similar to the plot labeled “Current Limit with Peaking” in

peaking in the current limit, corresponding to the characteristic labeled “Flat Current Limit” in Figure 21. This is

Figure 21. Current Limit Profiles

FLT

The FLT open-drain output is asserted (active low) during an over-load or over-temperature condition. A 8 ms

deglitch on both the rising and falling edged avoids false reporting at startup and during transients. A current limit

condition shorter than the deglitch period clears the internal timer upon termination. The deglitch timer will not

the ripple will drive the TPS2530 in and out of current limit.

If the TPS2530 is in current limit and the over-temperature circuit goes active, FLT goes true immediately

however exiting this condition is deglitched. FLT is tripped just as the knee of the constant-current limiting is

entered. Disabling the TPS2530 clears and active FLT as soon as the switch turns off. FLT is high impedance

when the TPS2530 is disabled or in undervoltage lockout (UVLO).

APPLICATION INFORMATION

INPUT AND OUTPUT CAPACITANCE

Input and output capacitance improves the performance of the device. The actual capacitance should be

optimized for the particular application. For all applications, a 0.1 µF or greater ceramic bypass capacitor

between IN and GND is recommended as close to the device as possible for local noise de-coupling.

All protection circuits such as TPS2530 will have the potential for input voltage overshoots and output voltage

undershoots.

Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input

voltage in conjunction with input power bus inductance and input capacitance when the IN terminal is high

impedance (before turn on). Theoretically, the peak voltage is 2 times the applied. The second cause is due to

the abrupt reduction of output short circuit current when the TPS2530 turns off and energy stored in the input

inductance drives the input voltage high. Input voltage droops may also occur with large load steps and as the

TPS2530 output is shorted. Applications with large input inductance (e.g. connecting the evaluation board to the

bench power-supply through long cables) may require large input capacitance reduce the voltage overshoot from

exceeding the absolute maximum voltage of the device. The fast current-limit speed of the TPS2530 to hard

output short circuits isolate the input bus form faults. However, ceramic input capacitance in the range of 1 µF to

22 µF adjacent to the TPS2530 input aids in both speeding response time and limiting the transient seen on the

input power bus. Momentary input transients to 6.5 V are permitted. In order to keep front-end power circuit work

normally, it is better to increase the output cap.

10

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