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TPS51462RGER Datasheet(PDF) 10 Page - Texas Instruments |
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TPS51462RGER Datasheet(HTML) 10 Page - Texas Instruments |
10 / 27 page = ´ OUT ON IN SW V 1 t V f + VSLEW + – RC + PWM Comparator RDS(on) GMV = 1 mS Driver LOUT ESR COUT ROUT UDG-11208 RLOAD 4 kW + – + GMC= 1 mS CC VREF TPS51462 SLUSAQ1 – DECEMBER 2011 www.ti.com PWM Frequency and Adaptive on Time Control In general, the on-time (at the SW node) can be estimated by Equation 1. where • fSW is the frequency selected by the connection of the MODE pin (1) The on-time pulse is sent to the top FET. The inductor current and the current feedback rises to peak value. Each ON pulse is latched to prevent double pulsing. Switching frequency settings are shown in Table 3. Non-Droop Configuration The TPS51462 offers a non-droop solution only. The benefit of a non-droop approach is that load regulation is flat, therefore, in a system where tight DC tolerance is desired, the non-droop approach is recommended. For the Intel system agent application, non-droop is recommended as the standard configuration. The non-droop approach can be implemented by connecting a resistor and a capacitor between the COMP and the VREF pins. The purpose of the type II compensation is to obtain high DC feedback gain while minimizing the phase delay at unity gain cross over frequency of the converter. The value of the resistor (RC) can be calculated using the desired unity gain bandwidth of the converter, and the value of the capacitor (CC) can be calculated by knowing where the zero location is desired. An application tool that calculates these values is available from your local TI Field Application Engineer. Figure 3 shows the basic implementation of the non-droop mode using the TPS51462. Figure 3. Non-Droop Mode Basic Implementation 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS51462 |
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