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TPS65072TRSLRQ1 Datasheet(PDF) 6 Page - Texas Instruments |
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TPS65072TRSLRQ1 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 90 page TPS65070-Q1, TPS65072-Q1, TPS65073-Q1, TPS650732-Q1 SLVSAP7 – JANUARY 2011 www.ti.com DCDC2 CONVERTER (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT For DEFDCDC2 = LOW 1.8 Default output voltage for TPS65070, TPS650732 For DEFDCDC2 = HIGH 3.3 For DEFDCDC2 = LOW 1.8 Vout Default output voltage for TPS65072 V For DEFDCDC2 = HIGH 2.5 For DEFDCDC2 = LOW 1.2 Default output voltage for TPS65073, TPS650731 For DEFDCDC2 = HIGH 1.8 DC output voltage accuracy; PFM mode (1) –2% 3% VINDCDC2 = 2.8 V to 6.3 V; –1.5 0 mA ≤ IO ≤ 1.5 A DC output voltage accuracy; PWM mode (1) 1.5% % Vout DC output voltage accuracy with resistor divider at DEFDCDC2; PFM –2% 3% VINDCDC2 = VDCDC2 +0.3 V (min 2.8 V) to 6.3 V; 0 mA ≤ IO ≤ 1.5A DC output voltage accuracy with resistor divider at DEFDCDC2; PWM –1% 1% ΔVOUT Power save mode ripple voltage IOUT = 1 mA, PFM mode (2) 40 mVpp Time from active EN to Start tStart Start-up time 170 ms switching Time to ramp from 5% to 95% of tRamp VOUT ramp up time 250 ms VOUT Vo - power good threshold rising voltage 5% Vo - power good threshold falling voltage 10% RDIS Internal discharge resistor at L2 –35% 250 35% Ω (1) Output voltage specification does not include tolerance of external voltage programming resistors. Output voltage in PFM mode is scaled to +1% of nominal value. (2) Configuration L= 2.2 mH, COUT = 10 mF DCDC3 CONVERTER PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VVINDCDC Input voltage range Connected to SYS pin 2.8 6.3 V 3 TPS65072 600 IO Maximum output current Vin > 2.8 V mA TPS65070, TPS65073, TPS650731, 1500 TPS650732 VINDCDC3 = 2.8 V 150 300 RDS(ON) High side MOSFET on-resistance m Ω VINDCDC3 = 3.5 V 120 200 ILH High side MOSFET leakage current VINDCDC3 = 6.3 V 2 mA VINDCDC3 = 2.8 V 200 300 RDS(ON) Low side MOSFET on-resistance m Ω VINDCDC3 = 3.5 V 160 180 ILL Low side MOSFET leakage current VDS = 6.3 V 1 mA TPS65072 0.8 1.1 1.5 ILIMF Forward current limit 2.8 V < VINDCDC3 < 6.3 V A TPS65070/73/731/732 2.1 2.4 3.5 fS Oscillator frequency 1.95 2.35 2.55 MHz Vout Adjustable output voltage range External resistor divider 0.6 Vin V Vref Reference voltage 600 mV Internal resistor divider, I2C Vout Fixed output voltage range 0.725 3.3 V selectable (Default setting) For DEFDCDC3 = LOW 1.0 Default output voltage for TPS65070 For DEFDCDC3 = HIGH 1.2 For DEFDCDC3 = LOW 1.2 Vout Default output voltage for TPS65072 V For DEFDCDC3 = HIGH 1.4 For DEFDCDC3 = LOW 1.2 Default output voltage for TPS65073, TPS650731, TPS650732 For DEFDCDC3 = HIGH 1.35 DC output voltage accuracy; PFM mode (1) –2% 3% VINDCDC3 = 2.8 V to 6.3 V; Vout 0 mA ≤ IO ≤ 1.5 A DC output voltage accuracy; PWM mode (1) –1.5% 1.5% (1) Output voltage specification does not include tolerance of external voltage programming resistors. Output voltage in PFM mode is scaled to +1% of nominal value. 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS65070-Q1 TPS65072-Q1 TPS65073-Q1 TPS650732-Q1 |
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