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ADC1002S020HL Datasheet(PDF) 7 Page - Integrated Device Technology |
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ADC1002S020HL Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 18 page ADC1002S020_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 7 of 18 Integrated Device Technology ADC1002S020 Single 10 bits ADC, up to 20 MHz Vref(dif) differential reference voltage VRT VRB 1.9 2.1 3.0 V Iref reference current - 7.2 - mA Rlad ladder resistance - 290 - TCRlad ladder resistor temperature coefficient - 539 - m /K - 1860 - ppm Voffset offset voltage BOTTOM [2] - 135 - mV TOP [2] - 135 - mV Vi(p-p) peak-to-peak input voltage [3] 1.66 1.83 2.35 V Digital outputs D9 to D0 and IR (Referenced to VSSD) VOL LOW-level output voltage IO = 1 mA 0 - 0.5 V VOH HIGH-level output voltage IO = 1 mA VDDO 0.5 - VCCO V IOZ OFF-state output current 0.5 V < VO < VDDO 20 - +20 A Switching characteristics; Clock input CLK; see Figure 4[1] fclk(max) maximum clock frequency 20 - - MHz tw(clk)H HIGH clock pulse width 15 - - ns tw(clk)L LOW clock pulse width 15 - - ns Analog signal processing (fclk = 20 MHz) Linearity INL integral non-linearity ramp input; see Figure 6 - 1 2 LSB DNL differential non-linearity ramp input; see Figure 7 - 0.25 0.7 LSB Input set response; see Figure 8[4] ts(LH) LOW to HIGH settling time full-scale square wave - 4 6 ns ts(HL) HIGH to LOW settling time full-scale square wave - 4 6 ns Harmonics; see Figure 9[5] THD total harmonic distortion fi = 1 MHz - 63 - dB Signal-to-Noise ratio; see Figure 9[5] S/N signal-to-noise ratio without harmonics; fi = 1 MHz - 60 - dB Effective bits; see Figure 9[5] ENOB effective number of bits fi = 300 KHz - 9.5 - bits fi = 1 MHz - 9.3 bits fi = 3.58 MHz - 8.0 bits Table 6. Characteristics …continued VDDA = V7 to V9 = 3.3 V; VDDD = V4 to V3 = V18 to V19 = 3.3 V; VDDO = V20 to V21 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(p-p) = 1.83 V; CL = 20 pF; Tamb = 0 C to 70 C; typical values measured at Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit |
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