ADC1112D125HN-C1 datasheet(11/39 Pages) IDT

No. de pieza	ADC1112D125HN-C1

Descripción Electrónicos	Dual 11-bit ADC; CMOS or LVDS DDR digital outputs

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Fabricante Electrónico	IDT [Integrated Device Technology]

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ADC1112D125 3

Product data sheet

Rev. 03 — 2 July 2012

11 of 39

Integrated Device Technology

ADC1112D125

Dual 11-bit ADC: CMOS or LVDS DDR digital outputs

10.2 Clock and digital output timing

[1]

Typical values measured at VDDA =3V, VDDO =1.8 V, Tamb =25 C; minimum and maximum values are across the full temperature

range Tamb = 40 C to +85 C at VDDA =3 V, VDDO = 1.8 V; VINAP  VINAM = 1 dBFS; VINBP  VINBM = 1 dBFS; unless otherwise

specified.

[2]

Measured between 20 % to 80 % of VDDO.

[3]

Rise time measured from

50 mV to +50 mV; fall time measured from +50 mV to 50 mV.

Table 8.

Clock and digital output timing characteristics[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Clock timing input: pins CLKP and CLKM

fclk

clock frequency

100

-

125

MHz

tlat(data)

data latency time

-

14

-

clock

cycles

clk

clock duty cycle

DCS_EN = 1

30

50

70

%

DCS_EN = 0

45

50

55

%

td(s)

sampling delay time

-

0.8

-

ns

twake

wake-up time

-

76

-

s

CMOS mode timing: pins DA10 to DA0, DB10 to DB0 and DAV

tPD

propagation delay

DATA

-

3.9

-

ns

DAV

-

4.2

-

ns

tsu

set-up time

-

5.7

-

ns

th

hold time

-

1.4

-

ns

tr

rise time

DATA

[2] 0.5

-

2.4

ns

DAV

0.5

-

2.4

ns

tf

fall time

DATA

[2] 0.5

-

2.4

ns

LVDS DDR mode timing: pins DA9_DA10_P to LOW_DA0_P, DA9_DA10 M to LOW_DA0_M,

DB9_DB10_P to LOW_DB0_P, DB9_DB10_M to LOW_DB0_M, DAVP and DAVM

tPD

propagation delay

DATA

-

3.9

-

ns

DAV

-

4.2

-

ns

tsu

set-up time

-

1.4

-

ns

th

hold time

-

2.0

-

ns

tr

rise time

DATA

[3] 50

100

200

ps

DAV

50

100

200

ps

tf

fall time

DATA

[3] 50

100

200

ps

DAV

50

100

200

ps

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ADC1112D125HN-C1 Datasheet(PDF) 11 Page - Integrated Device Technology

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