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ADC1212D065HN-C1 Datasheet(PDF) 9 Page - Integrated Device Technology

No. de pieza ADC1212D065HN-C1
Descripción Electrónicos  Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs
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Fabricante Electrónico  IDT [Integrated Device Technology]
Página de inicio  http://www.idt.com
Logo IDT - Integrated Device Technology

ADC1212D065HN-C1 Datasheet(HTML) 9 Page - Integrated Device Technology

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ADC1212D_SER 3
© IDT 2012. All rights reserved.
Product data sheet
Rev. 03 — 2 July 2012
9 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
[1]
Typical values measured at VDDA =3V, VDDO =1.8 V, Tamb =25 C; minimum and maximum values are across the full temperature
range Tamb = 40 C to +85 C at VDDA =3 V, VDDO = 1.8 V; VINAP  VINAM = 1 dBFS; VINBP  VINBM = 1 dBFS; internal reference
mode; applied to CMOS and LVDS interface; unless otherwise specified.
Digital outputs, LVDS DDR mode: pins DA10_DA11_P to DA0_DA1_P, DA10_DA11_M to DA0_DA1_M,
DB10_DB11_P to DB0_DB1_P, DB10_DB11_M to DB0_DB1_M; DAVP and DAVM
Output levels, VDDO = 3 V only, RL = 100 
VO(offset)
output offset voltage
output buffer current set to
3.5 mA
-1.2
-
V
VO(dif)
differential output voltage
output buffer current set to
3.5 mA
-350
-
mV
CO
output capacitance
-
3
-
pF
Analog inputs: pins INAP, INAM, INBP and INBM
II
input current
5-
+5
A
RI
input resistance
-
19.8
-
k
CI
input capacitance
-
2.8
-
pF
VI(cm)
common-mode input voltage
VINAP =VINAM; VINBP =VINBM
0.9
1.5
2
V
Bi
input bandwidth
-
600
-
MHz
VI(dif)
differential input voltage
peak-to-peak
1
-
2
V
Common-mode output voltage: pins VCMA and VCMB
VO(cm)
common-mode output voltage
-
0.5VDDA
-V
IO(cm)
common-mode output current
-
4
-
mA
I/O reference voltage: pin VREF
VVREF
voltage on pin VREF
output
-
0.5 to 1
-
V
input
0.5
-
1
V
Accuracy
INL
integral non-linearity
1.25
0.25
+5
LSB
DNL
differential non-linearity
guaranteed no missing codes
0.95
0.5
+0.95
LSB
Eoffset
offset error
-
2-
mV
EG
gain error
-
0.5
-
%FS
MG(CTC)
channel-to-channel gain
matching
-1.1
-
%
Supply
PSRR
power supply rejection ratio
200 mV (p-p) on pin VDDA;
fi =DC
-
37
-
dB
Table 6.
Static characteristics[1] …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit


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