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ADS7863 Datasheet(PDF) 6 Page - Texas Instruments

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No. de pieza ADS7863
Descripción Electrónicos  Dual, 2MSPS, 12-Bit, 2 2 or 3 3 Channel, Simultaneous Sampling
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

ADS7863 Datasheet(HTML) 6 Page - Texas Instruments

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CHA0
-
REF
IN
REF
OUT
AGND
AV
DD
M1
CHB1+
BGND
BV
DD
SDOA
SDOB
BUSY
1
2
3
4
5
6
18
17
16
15
14
13
ADS7863
BGND
CHB1+
CHB1
-
CHB0+
CHB0
-
CHA1+
CHA1
-
CHA0+
CHA0
-
REF
IN
REF
OUT
AGND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
BV
DD
SDOA
SDOB
BUSY
CLOCK
CS
RD
CONVST
SDI
M0
M1
AV
DD
ADS7863
SBAS383E – JUNE 2007 – REVISED JANUARY 2011
www.ti.com
DEVICE INFORMATION
ADS7863IDBQ
ADS7863IRGE
SSOP-24 (DBQ)
4 x 4 QFN-24 (RGE)
(TOP VIEW)
(TOP VIEW)
PIN DESCRIPTIONS
PIN NUMBER
SSOP
QFN
NAME
DESCRIPTION
1
17
BGND
Buffer I/O ground. Connect to digital ground plane.
2
18
CHB1+
Noninverting analog input channel B1
3
19
CHB1–
Inverting analog input channel B1
4
20
CHB0+
Noninverting analog input channel B0
5
21
CHB0–
Inverting analog input channel B0
6
22
CHA1+
Noninverting analog input channel A1
7
23
CHA1–
Inverting analog input channel A1
8
24
CHA0+
Noninverting analog input channel A0
9
1
CHA0–
Inverting analog input channel A0
10
2
REFIN
Reference voltage input. A ceramic capacitor of 470nF (min) is required at this terminal.
11
3
REFOUT
Reference voltage output. The programmable internal voltage reference output is available on this pin.
12
4
AGND
Analog ground. Connect to analog ground plane.
13
5
AVDD
Analog power supply, 2.7V to 5.5V. Decouple to AGND with a 1mF ceramic capacitor.
14
6
M1
Mode pin 1. Selects between the SDOx digital outputs (see Table 8).
15
7
M0
Mode pin 0. Selects between analog input channels (see Table 8).
Serial data input. This pin allows the additional features of the ADS7863 to be used but can also be used
16
8
SDI
in ADS7861-compatible manner.
Conversion start. The ADC switches from the sample into the hold mode on the rising edge of CONVST,
17
9
CONVST
independent of the status of CLOCK. The conversion itself starts with the next rising edge of CLOCK.
18
10
RD
Read data. Synchronization pulse for the SDOx outputs and SDI input. RD only triggers when CS is low.
19
11
CS
Chip select. When low, the SDOx outputs are active; when high, the SDOx outputs 3-state.
20
12
CLOCK
External clock input
ADC busy indicator. BUSY goes high when the inputs are in hold mode and returns to low after the
21
13
BUSY
conversion has been finished.
22
14
SDOB
Serial data output for converter B. Data are valid on the falling edge of CLOCK.
Serial data output for converter A. When M1 is high, both SDOA and SDOB are active. Data are valid on
23
15
SDOA
the falling edge of CLOCK.
24
16
BVDD
Buffer I/O supply, 2.7V to 5.5V. Decouple to BGND with a 1mF ceramic capacitor.
6
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Product Folder Link(s): ADS7863


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