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DAC3152IRGZR Datasheet(PDF) 3 Page - Texas Instruments

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No. de pieza DAC3152IRGZR
Descripción Electrónicos  Dual-Channel, 10-/12-Bit, 500-MSPS Digital-to-Analog Converters (DACs)
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

DAC3152IRGZR Datasheet(HTML) 3 Page - Texas Instruments

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DAC3162
RGZ Package
48-QFN 7x7mm
(Top View)
36
D10P
D11N
D1P
D1N
D0P
D0N
NC
NC
NC
DVDD18
D7N
D7P
D8N
D8P
D9N
D9P
D10N
D11P
DACCLKN
DACCLKP
VFUSE
ATEST
SLEEPB
NC
DAC3152
DAC3162
www.ti.com
SLAS736D – NOVEMBER 2010 – REVISED AUGUST 2012
DAC3162 PINOUT AND PIN FUNCTIONS
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
ATEST
35
O
Factory use only. Leave unconnected for normal operation.
AVDD33
40, 43, 45
Analog supply voltage (3.3 V)
BIASJ
42
O
Full-scale output current bias. For 20-mA full-scale output current, connect a 960-
Ω resistor to GND.
Internal clock buffer supply voltage (1.8 V)
CLKVDD18
44
This supply can be shared with DIGVDD18.
LVDS positive-input data bits 0 through 11. Each positive/negative LVDS pair has an internal 100-
Ω termination
resistor. Data format relative to DACCLKP/N clock is double data rate (DDR) with two data transfers per
3, 5, 7, 9, 11, 13,
DACCLKP/N clock cycle. Dual channel data is interleaved on this bus.
D[11..0]P
16, 19, 21, 23,
I
25, 27
D11P is most-significant data bit (MSB) – pin 3
D0P is least-significant data bit (LSB) – pin 27
LVDS negative-input data bits 0 through 11. (See D[11:0]P description)
4, 6, 8, 10, 12,
D[11..0]N
14, 17, 20, 22,
I
D11N is most-significant data bit (MSB) – pin 4
24, 26, 28
D0N is least-significant data bit (LSB) – pin 28
Positive external LVPECL clock input with a self-bias of approximately CLKVDD18/2. Input data is latched on both
DACCLKP
1
I
edges of DACCLKP/N (double data rate). The LVPECL clock signal should be AC coupled.
Complementary external LVPECL clock input (see the DACCLKP description). The LVPECL clock signal should
DACCLKN
2
I
be AC coupled.
Digital supply voltage (1.8 V)
DVDD18
15, 33, 41
This supply can be shared with CLKVDD18.
39, 46,
GND
Pins 39, 46 and the thermal pad located on the bottom of the QFN package are ground for all supplies.
Thermal pad
A-channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full-scale
IOUTAP
48
O
current sink and the least-positive voltage on the IOUTAP pin. Similarly, a 0xFFF data input results in a 0-mA
current sink and the most-positive voltage on the IOUTAP pin.
A-channel DAC complementary current output. IOUTAN has the opposite behavior of the IOUTAP described for
IOUTAN
47
O
IOUTAP. An input data value of 0x0000 results in a 0-mA sink and the most-positive voltage on the IOUTAN pin.
IOUTBP
37
O
B-channel DAC current output. See the IOUTAP description.
IOUTBN
38
O
B-channel DAC complementary current output. See the IOUTAN description.
NC
25–32
No connect. Leave unconnected for normal operation.
SLEEPB
34
I
Connect to GND to put the device in sleep mode or to AVDD for active mode. Internal pullup.
Digital supply voltage (1.8 V). This supply pin is also used for factory fuse programming. Connect to DVDD18
VFUSE
36
pins for normal operation.
VREF
18
I/O
Factory use only. Connect to a 0.1-
μF decoupling capacitor to GND.
Copyright © 2010–2012, Texas Instruments Incorporated
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