2

1

3

4

7

8

6

5

FB/DNC

PG

GND

OUT

EN

NC

DELAY

IN

TPS7A16

www.ti.com

SBVS171A

– DECEMBER 2011 – REVISED DECEMBER 2011

PIN CONFIGURATION

DGN PACKAGE

MSOP-8

(TOP VIEW)

PIN DESCRIPTIONS

TPS7A16xx

NAME

NO.

DESCRIPTION

DELAY

7

Delay pin. Connect a capacitor to GND to adjust the PG delay time; leave open if the reset function is not needed.

Enable pin. This pin turns the regulator on or off.

EN

5

For the adjustable version (TPS7A1601), the feedback pin is the input to the control-loop error amplifier. This pin is

used to set the output voltage of the device when the regulator output voltage is set by external resistors.

FB/DNC

2

For the fixed voltage versions: DO NOT CONNECT to this pin. Do not route this pin to any electrical net, not even

GND or IN.

GND

4

Ground pin.

Regulator input supply pin. A capacitor

> 0.1 µF must be tied from this pin to ground to assure stability. It is

recommended to connect a 10

µF ceramic capacitor from IN to GND (as close to the device as possible) to reduce

IN

8

circuit sensitivity to printed-circuit-board (PCB) layout, especially when long input tracer or high source impedances

are encountered.

NC

6

This pin can be left open or tied to any voltage between GND and IN.

Regulator output pin. A capacitor

> 2.2 µF must be tied from this pin to ground to assure stability. It is recommended

OUT

1

to connect a 10

µF ceramic capacitor from OUT to GND (as close to the device as possible) to maximize AC

performance.

PG

3

Power-good pin. Open collector output; leave open or connect to GND if the power-good function is not needed.

Solder to printed circuit board (PCB) to enhance thermal performance. Although it can be left floating, it is highly

PowerPAD

recommended to connect the PowerPAD to the GND plane.

Copyright

© 2011, Texas Instruments Incorporated

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Product Folder Link(s): TPS7A16