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TPS7A1601QDGNRQ1 Datasheet(PDF) 11 Page - Texas Instruments |
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TPS7A1601QDGNRQ1 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 26 page TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 www.ti.com SBVS188B – MARCH 2012 – REVISED MAY 2012 Table 1. Selected Resistor Combinations VOUT R1 R2 VOUT/(R1 + R2) « IQ NOMINAL ACCURACY 1.194 V 0 Ω ∞ 0 µA ±2% 1.8 V 1.18 M Ω 2.32 M Ω 514 nA ±(2% + 0.14%) 2..5 V 1.5 M Ω 1.37 M Ω 871 nA ±(2% + 0.16%) 3.3 V 2 M Ω 1.13 M Ω 1056 nA ±(2% + 0.35%) 5 V 3.4 M Ω 1.07 M Ω 1115 nA ±(2% + 0.39%) 10 V 7.87 M Ω 1.07 M Ω 1115 nA ±(2% + 0.42%) 12 V 14.3 M Ω 1.58 M Ω 755 nA ±(2% + 0.18%) 15 V 42.2 M Ω 3.65 M Ω 327 nA ±(2% + 0.19%) 18 V 16.2 M Ω 1.15 M Ω 1038 nA ±(2% + 0.26%) Close attention must be paid to board contamination when using high-value resistors; board contaminants may significantly impact voltage accuracy. If board cleaning measures cannot be ensured, consider using a fixed- voltage version of the TPS7A16 or using resistors in the order of hundreds or tens of k Ω. CAPACITOR RECOMMENDATIONS Low equivalent-series-resistance (ESR) capacitors should be used for the input, output, and feed-forward capacitors. Ceramic capacitors with X7R and X5R dielectrics are preferred. These dielectrics offer more stable characteristics. Ceramic X7R capacitors offer improved overtemperature performance, while ceramic X5R capacitors are the most cost-effective and are available in higher values. Note that high-ESR capacitors may degrade PSRR. INPUT AND OUTPUT CAPACITOR REQUIREMENTS The TPS7A16xx-Q1 ultralow-power, high-voltage linear regulators achieve stability with a minimum input capacitance of 0.1 µF and output capacitance of 2.2 µF; however, it is recommended to use a 10-µF ceramic capacitor to maximize ac performance. POWER-GOOD The power-good (PG) pin is an open-drain output and can be connected to any 5.5-V or lower rail through an external pullup resistor. When no CDELAY is used, the PG output is high-impedance when VOUT is greater than the PG trip threshold (VIT). If VOUT drops below VIT, the open-drain output turns on and pulls the PG output low. If output voltage monitoring is not needed, the PG pin can be left floating or connected to GND. To ensure proper operation of the power-good feature, maintain VIN ≥ 3 V (VIN_MIN). Power-Good Delay and Delay Capacitor The power-good delay time (tDELAY) is defined as the time period from when VOUT exceeds the PG trip threshold voltage (VIT) to when the PG output is high. This power-good delay time is set by an external capacitor (CDELAY) connected from the DELAY pin to GND; this capacitor is charged from 0 V to ap 1.8 V by the DELAY pin current (IDELAY) once VOUT exceeds the PG trip threshold (VIT). When CDELAY is used, the PG output is high-impedance when VOUT exceeds VIT, and VDELAY exceeds VREF. The power-good delay time can be calculated using: tDELAY = (CDELAY × VREF)/IDELAY. For example, when CDELAY = 10 nF, the PG delay time is approximately 12 ms; that is, (10 nF × 1.193 V)/1 µA = 11.93 ms. FEED-FORWARD CAPACITOR Although a feed-forward capacitor (CFF) from OUT to FB is not needed to achieve stability, it is recommended to use a 0.01-µF feed-forward capacitor to maximize ac performance. TRANSIENT RESPONSE As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but increases the duration of the transient response. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): TPS7A1601-Q1 TPS7A1633-Q1 TPS7A1650-Q1 |
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