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TPS7A4101DGNT Datasheet(PDF) 2 Page - Texas Instruments

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No. de pieza TPS7A4101DGNT
Descripción Electrónicos  50-V Input Voltage, 50-mA, Very High Voltage LINEAR REGULATOR
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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TPS7A4101DGNT Datasheet(HTML) 2 Page - Texas Instruments

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TPS7A41
SBVS183
– DECEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT
VOUT
TPS7A4101 yyy z
YYY is package designator.
Z is package quantity.
(1)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
Over operating free-air temperature range (unless otherwise noted).
VALUE
MIN
MAX
UNIT
IN pin to GND pin
–0.3
+55
V
OUT pin to GND pin
–0.3
+55
V
OUT pin to IN pin
–55
+0.3
V
Voltage
FB pin to GND pin
–0.3
+2
V
FB pin to IN pin
–55
+0.3
V
EN pin to IN pin
–55
0.3
EN pin to GND pin
–0.3
+55
V
Current
Peak output
Internally limited
Operating virtual junction, TJ
–40
+125
°C
Temperature
Storage, Tstg
–65
+150
°C
Human body model (HBM)
2.5
kV
Electrostatic discharge rating
Charged device model (CDM)
500
V
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
TPS7A4001
THERMAL METRIC(1)
DGN
UNITS
8 PINS
θJA
Junction-to-ambient thermal resistance
55.09
θJC(top)
Junction-to-case(top) thermal resistance
8.47
θJB
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
0.36
ψJB
Junction-to-board characterization parameter
14.6
θJC(bottom)
Junction-to-case(bottom) thermal resistance
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
DISSIPATION RATINGS
DERATING FACTOR
TA ≤ +25°C POWER
TA = +70°C POWER
TA = +85°C POWER
BOARD
PACKAGE
RθJA
RθJC
ABOVE TA = +25°C
RATING
RATING
RATING
High-K(1)
DGN
55.9
°C/W
8.47
°C/W
16.6mW/
°C
1.83W
1.08W
0.833W
(1)
The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch multilayer board with 2-ounce internal power and
ground planes and 2-ounce copper traces on top and bottom of the board.
2
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Copyright
© 2011, Texas Instruments Incorporated
Product Folder Link(s): TPS7A41


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