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TPS7A6533QKVURQ1 Datasheet(PDF) 11 Page - Texas Instruments |
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TPS7A6533QKVURQ1 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 18 page 30 35 40 45 50 55 0 200 400 600 800 1000 Thermal Pad Area (sq. mm) KVU (DPAK) (JESD 51-3) PCB Thermal Land Pad Exposed Tab Thermal Via (a) Before soldering (b) After soldering Ground Plane TPS7A6533-Q1 TPS7A6550-Q1 www.ti.com SLVSA98C – MAY 2010 – REVISED JULY 2012 Keeping other factors constant, the surface area of the thermal land pad contributes to heat dissipation only to a certain extent. Figure 12 shows the variation of θJA with surface area of the thermal land pad (soldered to the exposed pad) for the KVU package. Figure 11. Using a Multilayer PCB and Thermal Vias For Adequate Heat Dissipation Figure 12. θJA versus Thermal Pad Area Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): TPS7A6533-Q1 TPS7A6550-Q1 |
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