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TPS71H01 Datasheet(PDF) 30 Page - Texas Instruments |
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TPS71H01 Datasheet(HTML) 30 Page - Texas Instruments |
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30 / 45 page  TPS71H01Q, TPS71H33Q, TPS71H48Q, TPS71H50Q LOW DROPOUT VOLTAGE REGULATORS SLVS152B − NOVEMBER 1996 − REVISED AUGUST 2002 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THERMAL INFORMATION thermally enhanced TSSOP-20 (continued) If the system implements a TPS71H33QPWP regulator, where VI = 6 V and IO = 500 mA, the internal power dissipation is: P D(total) + V I * V O I O + (6 * 3.3) 0.5 + 1.35 W Comparing PD(total) with PD(max) reveals that the power dissipation in this example does not exceed the calculated limit. When it does, one of two corrective actions should be made: raising the power-dissipation limit by increasing the airflow or the heat-sink area, or lowering the internal power dissipation of the regulator by reducing the input voltage or the load current. In either case, the above calculations should be repeated with the new system parameters. mounting information Since the thermal pad is not a primary connection for an electrical signal, the importance of the electrical connection is not significant. The primary requirement is to complete the thermal contact between the thermal pad and the PWB metal. The thermal pad is a solderable surface and is fully intended to be soldered at the time the component is mounted. Although voiding in the thermal-pad solder-connection is not desirable, up to 50% voiding is acceptable. The data included in Figures 47 and 48 is for soldered connections with voiding between 20% and 50%. The thermal analysis shows no significant difference resulting from the variation in voiding percentage. Figure 50 shows the solder-mask land pattern for the PWP package. The minimum recommended heat-sink area is also illustrated. This is simply a copper plane under the body extent of the package, including metal routed under terminals 1, 2, 9, 10, 11, 12, 19, and 20. reliability information This section includes demonstrated reliability test results obtained from the qualification program. Accelerated tests are performed at high-stress conditions so that product reliability can be established during a relatively short test duration. Specific stress conditions are chosen to represent accelerated versions of various device- application environments and allow meaningful extrapolation to normal operating conditions. component level reliability test results preconditioning Preconditioning of components prior to reliability testing is employed to simulate the actual board assembly process used by the customer. This ensures that reliability test results are more representative of those that would be seen in the final application. The general form of the preconditioning sequence includes a moisture soak followed by multiple vapor-phase-reflow or infrared-reflow solder exposures. All components used in the following reliability tests were preconditioned in accordance with JEDEC Test Method A113 for Level 1 (not moisture-sensitive) products. Figure 50. PWP Package Land Pattern 1.2 mm 0.65 mm 0.27 mm 5.72 mm Location of Exposed Thermal Pad on PWP Package Minimum Recommended Heat-Sink Area |
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