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TPS3896PDRYR Datasheet(PDF) 3 Page - Texas Instruments

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No. de pieza TPS3896PDRYR
Descripción Electrónicos  Single-Channel, Adjustable Supervisory Circuit in Ultra-Small Package
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

TPS3896PDRYR Datasheet(HTML) 3 Page - Texas Instruments

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TPS3895, TPS3896
TPS3897, TPS3898
www.ti.com
SBVS172A
– JULY 2011 – REVISED SEPTEMBER 2011
ELECTRICAL CHARACTERISTICS
Over the operating temperature range of TJ = –40°C to +125°C, and 1.7 V < VCC< 6.5 V, unless otherwise noted. Typical
values are at TJ = +25°C and VCC = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TJ = –40°C to +125°C
1.7
6.5
V
VCC
Supply voltage range
TJ = 0°C to +85°C
1.65
6.5
V
V(POR)
Power-on reset voltage(1)
VOL (max) = 0.2 V , I(SENSE_OUT) = 15 µA
0.8
V
VCC = 3.3 V , no load
6
12
µA
ICC
Supply current (into VCC pin)
VCC = 6.5 V , no load
7
12
µA
VIT+
Positive-going input threshold voltage
V(SENSE) rising
0.495
0.5
0.505
V
Vhys
Hysteresis voltage
V(SENSE) falling
5
mV
I(SENSE)
Input current(2)
V(SENSE) = 0 V or VCC
–15
15
nA
I(CT)
CT pin charge current
260
310
360
nA
V(CT)
CT pin comparator threshold voltage
1.180
1.238
1.299
V
R(CT)
CT pin pull-down resistance
200
Ω
VIL
Low-level input voltage (ENABLE pin)
0.4
V
VIH
High-level input voltage (ENABLE pin)
1.4
V
UVLO
Undervoltage lockout(3)
VCC falling
1.3
1.7
V
Ilkg
Leakage current
ENABLE = VCC or GND
–100
100
nA
VCC ≥ 1.2 V, ISINK = 90 µA (TPS3895/7 only)
0.3
V
VOL
Low-level output voltage
VCC ≥ 2.25 V, ISINK = 0.5 mA
0.3
V
VCC ≥ 4.5 V, ISINK = 1 mA
0.4
V
VCC ≥ 2.25 V, ISOURCE = 0.5 mA
0.8VCC
V
VOH
High-level output voltage (push-pull)
VCC ≥ 4.5 V, ISOURCE = 1 mA
0.8VCC
V
Ilkg(OD)
Open-drain output leakage current
V(SENSE_OUT) high impedance = 18 V
300
nA
V(SENSE) rising, C(CT) = open
40
µs
SENSE (rising) to SENSE_OUT
tpd(r)
propagation delay
V(SENSE) rising, C(CT) = 0.047 µF
190
ms
SENSE (falling) to SENSE_OUT
tpd(f)
V(SENSE) falling
16
µs
propagation delay
Startup delay(4)
50
µs
tw
ENABLE pin minimum pulse duration
1
µs
ENABLE pin glitch rejection
100
ns
ENABLE to SENSE_OUT delay time
td(off)
ENABLE de-asserted to output de-asserted
200
ns
(output disabled)
ENABLE to SENSE_OUT delay time
ENABLE asserted to output asserted delay
td(P)
200
ns
(P version)
(P version)
ENABLE asserted to output asserted delay
20
µs
(A version), C(CT) = open
ENABLE to SENSE_OUT delay time
td(A)
(A version)
ENABLE asserted to output asserted delay
190
ms
(A version), C(CT) = 0.047 µF
(1)
The lowest supply voltage (VCC) at which output is active (SENSE_OUT is low, SENSE_OUT is high); tr(VCC) > 15 µs/V. Below V(POR),
the output cannot be determined.
(2)
Specified by design.
(3)
When VCC falls below the UVLO threshold, the output de-asserts (SENSE_OUT goes low, SENSE_OUT goes high). Below V(POR), the
output cannot be determined.
(4)
During power on, VCC must exceed 1.7 V for at least 50 µs (plus propagation delay time, tpd(r)) before output is in the correct state.
Copyright
© 2011, Texas Instruments Incorporated
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Product Folder Link(s): TPS3895 TPS3896 TPS3897 TPS3898


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