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TPS3897PDRYT Datasheet(PDF) 2 Page - Texas Instruments

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No. de pieza TPS3897PDRYT
Descripción Electrónicos  Single-Channel, Adjustable Supervisory Circuit in Ultra-Small Package
Download  21 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

TPS3897PDRYT Datasheet(HTML) 2 Page - Texas Instruments

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TPS3895, TPS3896
TPS3897, TPS3898
SBVS172A
– JULY 2011 – REVISED SEPTEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT
DESCRIPTION
TPS389wxyyyz
w is output configuration (see Table 1)
x is different delay from enable pin (see Table 1)
yyy is package designator
z is package quantity
(1)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
Over operating free-air temperature range (unless otherwise noted).
VALUE
MIN
MAX
UNIT
VCC
–0.3
7
V
CT
–0.3
VCC + 0.3
V
Voltage(2)
ENABLE, SENSE, SENSE_OUT (push-pull)
–0.3
7
V
SENSE_OUT (open-drain)
–0.3
20
V
Current
SENSE_OUT
±10
mA
Operating junction, TJ
–40
+125
°C
Temperature
Storage, Tstg
–65
+150
°C
Human body model (HBM)
2
kV
Electrostatic discharge rating(3)
Charge device model (CDM)
500
V
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2)
All voltages are with respect to network ground terminal.
(3)
ESD testing is performed according to the respective JESD22 JEDEC standard.
THERMAL INFORMATION
TPS389x
THERMAL METRIC(1)
DRY (
µSON)
UNITS
6 PINS
θJA
Junction-to-ambient thermal resistance
293.8
θJCtop
Junction-to-case (top) thermal resistance
165.1
θJB
Junction-to-board thermal resistance
160.8
°C/W
ψJT
Junction-to-top characterization parameter
27.3
ψJB
Junction-to-board characterization parameter
65.8
θJCbot
Junction-to-case (bottom) thermal resistance
65.8
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
Submit Documentation Feedback
Copyright
© 2011, Texas Instruments Incorporated
Product Folder Link(s): TPS3895 TPS3896 TPS3897 TPS3898


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