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TPS3106K33DBVTG4 Datasheet(PDF) 4 Page - Texas Instruments

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No. de Pieza. TPS3106K33DBVTG4
Descripción  UltraLow Supply-Current/Supply-Voltage Supervisory Circuits
Descarga  25 Pages
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Fabricante  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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TPS3106K33DBVTG4 Datasheet(HTML) 4 Page - Texas Instruments

 
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SWITCHING CHARACTERISTICS
TIMING REQUIREMENTS
TPS3103xxx
TPS3106xxx
TPS3110xxx
SLVS363E – AUGUST 2001 – REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MR
MR = 0 V, VDD = 3.3 V
–47
–33
–25
μA
IIL
Low-level input current
SENSE, PFI,
SENSE, PFI, WDI = 0 V,
–25
25
nA
WDI
VDD = 3.3 V
High-level output current
IOH
Open-drain
VDD = VIT + 0.2 V, VOH = 3.3 V
200
nA
at RESET(2)
VDD > VIT (average current),
1.2
3
VDD < 1.8 V
VDD > VIT (average current),
2
4.5
IDD
Supply current
μA
VDD > 1.8 V
VDD < VIT, VDD < 1.8 V
22
VDD < VIT, VDD > 1.8 V
27
Internal pull-up resistor at MR
70
100
130
k
CI
Input capacitance at MR, SENSE, PFI, WDI VI = 0 V to VDD
1
pF
(2)
Also refers to RSTVDD and RSTSENSE.
At RL = 1 MΩ, CL = 50 pF, and TA = –40°C to +85°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tD
Delay time
VDD ≥ 1.1 × VIT, MR = 0.7 × VDD, See Timing Diagrams
65
130
195
ms
Propagation delay time,
VDD to RESET or
tPHL
VIH = 1.1 × VIT, VIL = 0.9 × VIT
40
μs
high-to-low level output
RSTVDD delay
Propagation delay time,
VDD to RESET or
tPLH
VIH = 1.1 × VIT, VIL = 0.9 × VIT
40
μs
low-to-high level output
RSTVDD delay
Propagation delay time,
SENSE to RESET or
tPHL
VDD ≥ 0.8 V, VIH = 1.1 × VIT, VIL = 0.9 × VIT
40
μs
high-to-low level output
RSTSENSE delay
Propagation delay time,
SENSE to RESET or
tPLH
VDD ≥ 0.8 V, VIH = 1.1 × VIT, VIL = 0.9 × VIT
40
μs
high-to-low level output
RSTSENSE delay
Propagation delay time,
tPHL
PFI to PFO delay
VDD ≥ 0.8 V, VIH = 1.1 × VIT, VIL = 0.9 × VIT
40
μs
high-to-low level output
Propagation delay time,
tPLH
PFI to PFO delay
VDD ≥ 0.8 V, VIH = 1.1 × VIT, VIL = 0.9 × VIT
300
μs
low-to-high level output
MR to RESET.
Propagation delay time,
tPHL
RSTVDD,
VDD ≥ 1.1 × VIT, VIL = 0.3 × VDD, VIH = 0.7 × VDD
1
5
μs
low-to-high level output
RSTSENSE delay
MR to RESET.
Propagation delay time,
tPLH
RSTVDD,
VDD ≥ 1.1 × VIT, VIL = 0.3 × VDD, VIH = 0.7 × VDD
1
5
μs
low-to-high level output
RSTSENSE delay
At RL = 1 MΩ, CL = 50 pF, and TA = –40°C to +85°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tT(OUT)
Time-out period
at WDI
VDD ≥ 0.85 V
0.55
1.1
1.65
s
at VDD
VIH = 1.1 × VIT, VIL = 0.9 × VIT–, VIT– = 0.86 V
20
at MR
VDD ≥ VIT + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD
0.1
tW
Pulse width
at SENSE
VDD ≥ VIT, VIH = 1.1 × VIT − (S), VIL = 0.9 × VIT − (S)
20
μs
at PFI
VDD ≥ 0.85 V, VIH = 1.1 × VIT − (S),VIL = 0.9 × VIT − (S)
20
at WDI
VDD ≥ VIT, VIL = 0.3 × VDD, VIH = 0.7 × VDD
0.3
4
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