TPS22933

www.ti.com

SLVSB34

– OCTOBER 2011

APPLICATION INFORMATION

POWER CHANGEOVER

The TPS22933 LDO is powered by the highest level input. When input voltages change, the TPS22933 may

change which input powers the LDO. During initial power up, the input that reaches the highest value first will

power the LDO. Once that decision is made, changing between input sources is based on VCO. When an input

source becomes VCO over the input currently supplying power to the LDO, changeover will occur and the new,

higher input will power the LDO.

TPS22933A EXAMPLE:

Initial power up:

DC_IN = 0V; USB = 0V; EN = 0V

BAT is applied at 4.2V

LDO power comes from BAT

LOUT = 3.6V; CAP = 4.2V; VOUT = 0V

USB power is connected at 5.0V, BAT remains 4.2V and DC_IN remains 0V

LOUT = 3.6V; CAP = 5.0V; VOUT = 0V

DC_IN power is connected at 5.0V, BAT remains 4.2V and USB remains 5V

No change in LDO power

LOUT = 3.6V; CAP = 5.0V; VOUT = 0V

EN = VIH, BAT remains 4.2V, USB remains 5.0V and DC_IN remains 5V

LOUT = 3.6V, CAP = 5.0V; VOUT = 3.6V

USB power is removed, BAT remains 4.2V and DC_IN remains 5.0V

LDO power is changed from USB to DC_IN

LOUT = 3.6V; CAP = 5.0V; VOUT = 3.6V

DC_IN power is removed, BAT remains 4.2V and USB remains 0V:

LDO power is changed from DC_IN to BAT

LOUT = 3.6V; CAP = 4.2V; VOUT = 3.6V

ON/OFF CONTROL

The EN pin controls the state of the VOUT switch and VOUT pull-down switch. EN has no control over LOUT.

Asserting EN enables the VOUT switch and disables the Quick Output Discharge (QOD) switch. Deasserting EN

disables the VOUT switch and enables the QOD switch. EN is active high and has a low threshold making it

capable of interfacing with low voltage signals. The EN pin is compatible with standard GPIO Logic threshold and

can be used with any microcontroller with 1.2-V, 1.8-V, 2.5-V or 3.3-V GPIOs.

LDO CAPACITOR (for CAP pin)

An optional capacitor on the CAP pin helps stabilize the integrated LDO. Care should be taken in capacitor sizing

to reduce inrush currents. The voltage on the CAP pin will follow the highest input. Since the max input voltage is

12-V, the capacitor voltage rating must be higher than 12-V.

BOARD LAYOUT

For best performance, all traces should be as short as possible. To be most effective, the input and output

capacitors should be placed close to the device to minimize the effects that parasitic trace inductances may have

on normal and short-circuit operation. Using wide traces for BAT, USB, DC_IN, LOUT, VOUT, and GND will help

minimize the parasitic electrical effects along with minimizing the case to ambient thermal impedance.

Copyright

© 2011, Texas Instruments Incorporated

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