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ISLA222S20IR1Z Datasheet(PDF) 7 Page - Intersil Corporation

No. de pieza ISLA222S20IR1Z
Descripción Electrónicos  Dual 12-Bit, 250/200/125 MSPS JESD204B High Speed Serial Output ADC
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Fabricante Electrónico  INTERSIL [Intersil Corporation]
Página de inicio  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISLA222S20IR1Z Datasheet(HTML) 7 Page - Intersil Corporation

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ISLA222S
7
FN8302.0
May 1, 2012
Signal-to-Noise and
Distortion (Note 10)
SINAD
fIN = 30MHz
70.5
71.1
71.7
dBFS
fIN = 105MHz
69.0
70.4
70.2
71.0
70.4
71.3
dBFS
fIN = 190MHz
70.0
70.5
70.7
dBFS
fIN = 363MHz
69.0
68.9
67.8
dBFS
fIN = 495MHz
65.4
64.0
61.4
dBFS
fIN = 605MHz
59.3
58.0
54.1
dBFS
Effective Number of Bits
(Note 10)
ENOB
fIN = 30MHz
11.42
11.52
11.61
Bits
fIN = 105MHz
11.17 11.40
11.37 11.50
11.40 11.55
Bits
fIN = 190MHz
11.34
11.42
11.46
Bits
fIN = 363MHz
11.16
11.16
10.97
Bits
fIN = 495MHz
10.57
10.34
9.91
Bits
fIN = 605MHz
9.56
9.35
8.69
Bits
Spurious-Free Dynamic
Range (Note 10)
SFDR
fIN = 30MHz
87
93
95
dBc
fIN = 105MHz
74
83
76
89
76
87
dBc
fIN = 190MHz
84
93
86
dBc
fIN = 363MHz
79
88
71
dBc
fIN = 495MHz
66
85
61
dBc
fIN = 605MHz
58
83
52
dBc
Spurious-Free Dynamic
Range Excluding H2, H3
(Note 10)
SFDRX23 fIN = 30MHz
87
93
98
dBc
fIN = 105MHz
89
95
96
dBc
fIN = 190MHz
88
93
90
dBc
fIN = 363MHz
84
88
85
dBc
fIN = 495MHz
85
85
82
dBc
fIN = 605MHz
88
83
81
dBc
Intermodulation
Distortion
IMD
fIN = 70MHz
-84
-82
-81
dBFS
fIN = 170MHz
-92
-99
-100
dBFS
Channel-to-Channel
Isolation
fIN = 10MHz
88
90
100
dB
fIN = 124MHz
82
87
86
dB
Word Error Rate
WER
10-13
10-13
10-13
Full Power Bandwidth
FPBW
675
675
675
MHz
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. PSRR is calculated by the equation 20*log10(A/B), where B is the amplitude of a disturber sinusoid on AVDD at the device pins, and A is the amplitude
of the spur in the captured data at the frequency of the disturber sinusoid.
8. AC Specifications apply after internal calibration of the ADC is invoked at the given sample rate and temperature. Refer to “Power-On Calibration” on
page 15 and “User Initiated Reset” on page 16 for more detail.
9. The DLL Range setting must be changed via SPI for ADC core sample rates below 80MSPS. The JESD204 transmitter can support ADC sample rates
below 100MSPS, as long as the SERDES lane data rate is greater than or equal to 1Gbps.
10. Minimum specification guaranteed when calibrated at +85°C.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply
over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITIONS
ISLA222S25
ISLA222S20
ISLA222S12
UNITS
MIN
(Note 6) TYP
MAX
(Note 6)
MIN
(Note 6) TYP
MAX
(Note 6)
MIN
(Note 6) TYP
MAX
(Note 6)


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