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SST58LD008 Datasheet(PDF) 5 Page - Silicon Storage Technology, Inc |
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SST58LD008 Datasheet(HTML) 5 Page - Silicon Storage Technology, Inc |
5 / 40 page Data Sheet ATA-Disk Chip SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 5 ©2001 Silicon Storage Technology, Inc. S71167-05-000 9/01 391 1.0 GENERAL DESCRIPTION The SST’s ATA-Disk Chip (ADC) contains a controller, embedded firmware and Flash Media in a 32-pin DIP pack- age. Refer to Figure 1-1 for SST’s ADC block diagram. The controller interfaces with the host system allowing data to be written to and read from the Flash Media. 1.1 Performance-optimized ATA Controller The heart of the ADC is the ATA controller which translates standard ATA signals into Flash Media data and controls. SST’s ADC contains a proprietary ATA controller that was specifically designed to attain high data throughput from host to Flash. The following components contribute to the ATA controller’s operation. 1.1.1 Microcontroller Unit (MCU) The MCU translates ATA commands into data and control signals required for flash memory operation. 1.1.2 Internal Direct Memory Access (DMA) The ATA controller inside ADC uses DMA allowing instant data transfer from buffer to memory. This implementation eliminates microcontroller overhead associated with tradi- tional, firmware based, memory control, increasing data transfer rate. 1.1.3 Power Management Unit (PMU) Power Management Unit controls the power consumption of the ADC. The PMU dramatically extends product battery life by putting the part of the circuitry that is not in operation into sleep mode. 1.1.4 SRAM Buffer A key contributor to the ATA controller performance is an SRAM buffer. The buffer optimizes host’s data writes to Flash Media. 1.1.5 Embedded Flash File System Embedded Flash File System is an integral part of the SST’s ATA controller. It contains MCU Firmware that per- forms the following tasks: 1. Translates host side signals into Flash Media Writes and Reads. 2. Provides Flash Media wear leveling to spread the Flash writes across all the memory address space to increase the longevity of Flash Media. 3. Keeps track of data file structures. 1.1.6 Error Correction Code (ECC) The ATA Controller contains ECC algorithm that corrects 3 Bytes of error per 512 Byte sector. FIGURE 1-1: SST ATA-DISK CHIP BLOCK DIAGRAM 391 ILL1-1.5 HOST ATA/IDE BUS ATA Controller Flash Media Embedded Flash File System MCU ECC Internal DMA SRAM Buffer PMU |
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