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SST89E554-25-C-TQI Datasheet(PDF) 22 Page - Silicon Storage Technology, Inc |
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SST89E554-25-C-TQI Datasheet(HTML) 22 Page - Silicon Storage Technology, Inc |
22 / 58 page 22 Preliminary Specifications FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 384 Symbol Function SPIF Upon completion of data transfer, this bit is set to 1. If SPIE =1 and ES =1, an interrupt is then generated. To clear, read SPSR and then access SPDR. WCOL Set if the SPI data register is written to during data transfer. To clear, read SPSR and then access SPDR. Symbol Function SMOD1 Double Baud rate bit. If SMOD1 = 1, Timer 1 is used to generate the baud rate. SMOD0 FE/SM0 Selection bit. 0: SCON[7] = SM0 1: SCON[7] = FE, BOF Brown-out detection status bit, this bit will not be affected by any other reset. BOF should be cleared by software. Power-on reset will also clear the BOF bit. 0: No Brown-out. 1: Brown-out occurred POF Power-on reset status bit, this bit will not be affected by any other reset. POF should be cleared by software. 0: No Power-on reset. 1: Power-on reset occurred GF1 General-purpose flag bit. GF0 General-purpose flag bit. PD Power-down bit. 0: Power-down mode is not activated. 1: Activates Power-down mode. IDL Idle mode bit. 0: Idle mode is not activated. 1: Activates Idle mode. SPI Status Register (SPSR) Location 76543210 Reset Value AAH SPIF WCOL - - ---- 00xxxxxxb SPI Data Register (SPDR) Location 76543210 Reset Value 86H SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 00H Power Control Register (PCON) Location 76543210 Reset Value 87H SMOD1 SMOD0 BOF POF GF1 GF0 PD IDL 00010000b |
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