SN74HC163Q1

4BIT SYNCHRONOUS BINARY COUNTER

SCLS584A − MAY 2004 − REVISED APRIL 2008

2

POST OFFICE BOX 655303

description/ordering information (continued)

This counter features a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that

modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of

the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the

stable setup and hold times.

logic diagram (positive logic)

1

9

10

7

3

15

14

CLR

LOAD

ENT

ENP

CLK

A

RCO

QA

† For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown

on the logic diagram of the D/T flip-flops.

M1

G2

G4

3D

4R

1, 2T/1C3

4

13

B

QB

M1

G2

G4

3D

4R

1, 2T/1C3

5

12

C

QC

M1

G2

G4

3D

4R

1, 2T/1C3

6

11

D

QD

M1

G2

G4

3D

4R

1, 2T/1C3

2

LD†

CK†

CK

R

LD