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SST89E564-40-C-TQI Datasheet(PDF) 50 Page - Silicon Storage Technology, Inc |
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SST89E564-40-C-TQI Datasheet(HTML) 50 Page - Silicon Storage Technology, Inc |
50 / 58 page 50 Preliminary Specifications FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 384 FIGURE 10-1: IDD TEST CONDITION, ACTIVE MODE FIGURE 10-2: IDD TEST CONDITION, IDLE MODE FIGURE 10-3: IDD TEST CONDITION, POWER-DOWN MODE FIGURE 10-4: IDD TEST CONDITION, STANDBY (STOP CLOCK) MODE 4. Capacitive loading on Ports 0 & 2 may cause the VOH on ALE and PSEN# to momentarily fall below the VDD - 0.7 specification when the address bits are stabilizing. 5. Pins of Ports 1, 2 & 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when Vin is approximately 2V. 6. Pin capacitance is characterized but not tested. EA# is 25pF (max). 7. See Figures 10-1, 10-2, 10-3 and 10-4 for test conditions. Minimum VDD for Power Down is 2.0V. VDD VDD VDD VDD P0 EA# RST XTAL2 (NC) CLOCK SIGNAL All other pins disconnected 89x564 XTAL1 384 ILL F26.2 VSS IDD VDD VDD VDD P0 EA# RST XTAL2 (NC) CLOCK SIGNAL All other pins disconnected XTAL1 384 ILL F24.2 VSS IDD 89x564 VDD VDD VDD VDD = 2V P0 EA# RST XTAL2 (NC) All other pins disconnected XTAL1 384 ILL F25.2 VSS IDD 89x564 VDD VDD VDD VDD = 5V P0 EA# RST XTAL2 (NC) All other pins disconnected XTAL1 384 ILL F33.2 VSS IDD 89x564 |
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