 |
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
|
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
SST89E554-25-C-NJ Datasheet(PDF) 37 Page - Silicon Storage Technology, Inc |
|
||||||||||||||||||||||||||||||
SST89E554-25-C-NJ Datasheet(HTML) 37 Page - Silicon Storage Technology, Inc |
|
|
37 / 58 page  Preliminary Specifications FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 37 ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 384 AAR is only available when using the serial port in either mode 2 or 3. Setting the SM2 bit in SCON enables AAR. Each slave must have its SM2 bit set when waiting for an address (9th bit = 1). The Receive Interrupt (RI) flag will only be set when the received byte matches either the Given or Broadcast Address. The slave then clears its SM2 bit to enable reception of data bytes (9th bit = 0) from the master. The master can selectively communicate with groups of slaves by sending the Given Address. Addressing all slaves is also possible by sending the Broadcast address. The SADDR and SADEN special function registers define these addresses for each slave. SADDR specifies a slaves individual address and SADEN is a mask byte that defines don’t-care bits to form the Given address when combined with SADDR. The following is an example: In this example Slave 1 can be distinguished from Slave 2 by using bits 0 and 1. Slave 1 will not respond to an address that has bit 1 set to 1 while Slave 2 will. Similarly, Slave 2 will not respond to an address that has bit 0 set to 0 while Slave 1 will. Both slaves will respond to an address of 1111 0x01b so this is the Broadcast Address. The Broad- cast Addresses is formed by the logical OR of SADDR and SADEN with 0s treated as don’t-care bits. 6.2 Serial Peripheral Interface (SPI) The device SPI allows for high-speed full-duplex synchro- nous data transfer between the device and other compati- ble SPI devices. Figure 6-1 shows the correspondence between master and slave SPI devices. The SCK pin is the clock output and input for the master and slave modes, respectively. The SPI clock generator will start following a write to the master devices SPI data register. The written data is then shifted out of the MOSI pin on the master device into the MOSI pin of the slave device. Following a complete transmission of one byte of data, the SPI clock generator is stopped and the SPIF flag is set. An SPI interrupt request will be gener- ated if the SPI interrupt enable bit (SPIE) and the serial port interrupt enable bit (ES) are both set. An external master drives the Slave Select input pin, SS#/ P1[4], low to select the SPI module as a slave. If SS#/P1[4] has not been driven low, then the slave SPI unit is not active and the MOSI/P1[5] port can also be used as an input port pin. CPHA and CPOL control the phase and polarity of the SPI clock. Figures 6-2 and 6-3 show the four possible combina- tions of these two bits. FIGURE 6-1: SPI MASTER-SLAVE INTERCONNECTION UART Slave 1 SADDR = 1111 0001 SADEN = 1111 1010 GIVEN = 1111 0x0x UART Slave 2 SADDR = 1111 0011 SADEN = 1111 1001 GIVEN = 1111 0xx1 384 ILL F53.1 8-bit Shift Register MSB MASTER LSB SPI Clock Generator MISO MISO MOSI MOSI SCK SCK SS# SS# 8-bit Shift Register MSB SLAVE LSB VIH |
Número de pieza similar - SST89E554-25-C-NJ |
|
Descripción similar - SST89E554-25-C-NJ |
|
|
Enlace URL |
| Política de Privacidad |
| ALLDATASHEET.ES |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Spanish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
