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SST89E564-40-C-NJ Datasheet(PDF) 45 Page - Silicon Storage Technology, Inc |
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SST89E564-40-C-NJ Datasheet(HTML) 45 Page - Silicon Storage Technology, Inc |
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45 / 58 page  Preliminary Specifications FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 45 ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 384 TABLE 9-2: POWER SAVING MODES Mode Initiated by State of MCU Exited by Idle Mode Software (Set IDL bit in PCON) CLK is running. Interrupts, serial port and tim- ers/counters are active. Pro- gram Counter is stopped. ALE and PSEN# signals at a HIGH level during Idle. All registers remain unchanged. Enabled interrupt or hardware reset. Start of interrupt clears IDL bit and exits Idle mode, after the ISR RETI instruction, program resumes execu- tion beginning at the instruction follow- ing the one that invoked Idle mode. A user could consider placing two or three NOP instructions after the instruction that invokes idle mode to eliminate any problems. A hardware reset restarts the device similar to a power-on reset. Power Down Mode Software (Set PD bit in PCON) CLK is stopped. On-chip SRAM and SFR data is main- tained. ALE and PSEN# sig- nals at a LOW level during Power Down. External Inter- rupts are only active for level sensitive interrupts, if enabled. Enabled external level sensitive inter- rupt or hardware reset. Start of inter- rupt clears PD bit and exits Power Down mode, after the ISR RETI instruction program resumes execution beginning at the instruction following the one that invoked Power Down mode. A user could consider placing two or three NOP instructions after the instruction that invokes Power Down mode to eliminate any problems. A hardware reset restarts the device sim- ilar to a power-on reset. Standby (Stop Clock) Mode External hardware gates OFF the external clock input to the MCU. This gating should be synchronized with an input clock transition (low-to-high or high-to-low). CLK is frozen. On-chip SRAM and SFR data is maintained. ALE and PSEN# are main- tained at the levels prior to the clock being frozen. Gate ON external clock. Program exe- cution resumes at the instruction fol- lowing the one during which the clock was gated off. T9-2.6 384 |
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