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SST89E564-40-I-NJ Datasheet(PDF) 44 Page - Silicon Storage Technology, Inc |
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SST89E564-40-I-NJ Datasheet(HTML) 44 Page - Silicon Storage Technology, Inc |
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44 / 58 page  44 Preliminary Specifications FlashFlex51 MCU SST89E564 / SST89V564 / SST89E554 / SST89V554 ©2001 Silicon Storage Technology, Inc. S71181-03-000 9/01 384 9.5 Power-Saving Modes The device provides three power saving modes of opera- tion for applications where power consumption is critical. The three power saving modes are: Idle, Power Down and Standby (Stop Clock). 9.5.1 Idle Mode Idle mode is entered setting the IDL bit in the PCON regis- ter. In Idle mode, the program counter (PC) is stopped. The system clock continues to run and all interrupts and periph- erals remain active. The on-chip RAM and the special func- tion registers hold their data during this mode. The device exits Idle mode through either a system inter- rupt or a hardware reset. Exiting Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits Idle mode. After exit the Interrupt Service Routine, the interrupted program resumes execution beginning at the instruction immediately following the instruction which invoked the Idle mode. A hardware reset starts the device similar to a power-on reset. 9.5.2 Power Down Mode The Power Down mode is entered by setting the PD bit in the PCON register. In the Power Down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only. To retain the on-chip RAM and all of the spe- cial function registers’ values, the minimum VDD level is 2.0V. The device exits Power Down mode through either an enabled external level sensitive interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits Power Down. Holding the external interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bringing back high to complete the exit. After exit the interrupt service routine program execution resumes beginning at the instruction immediately following the instruction which invoked Power Down mode. A hard- ware reset starts the device similar to power-on reset. To exit properly out of Power Down, the reset or external interrupt should not be executed before the VDD line is restored to its normal operating voltage. Be sure to hold VDD voltage long enough at its normal operating level for the oscillator to restart and stabilize (normally less than 10 ms). 9.5.3 Standby Mode (Stop Clock) Standby mode is similar to Power Down mode, except that Power Down mode is initiated by a software command and Standby mode is initiated by external hardware gating off the external clock to the device.The on-chip SRAM and SFR data are maintained in Standby mode. The device resumes operation at the next instruction when the clock is reapplied to the part. Table 9-2 outlines the different power-saving modes, includ- ing entry and exit procedures and MCU functionality. TABLE 9-1: INTERRUPT POLLING SEQUENCE Description Interrupt Flag Vector Address Interrupt Enable Interrupt Priority Arbitration Ranking Wake-Up Power Down Ext. Int0 IE0 0003H EX0 PX0/H 1(highest) yes Brown-out BOF 004BH EBO PBO/H 2 no T0 TF0 000BH ET0 PT0/H 3 no Ext. Int1 IE1 0013H EX1 PX1/H 4 yes T1 TF1 001BH ET1 PT1/H 5 no UART/SPI TI/RI/SPIF 0023H ES PS/H 6 no T2 TF2, EXF2 002BH ET2 PT2/H 7 no T9-1.2 384 |
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