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TPS3807A30DCKT Datasheet(PDF) 4 Page - Texas Instruments |
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TPS3807A30DCKT Datasheet(HTML) 4 Page - Texas Instruments |
4 / 13 page www.ti.com FUNCTIONAL BLOCK DIAGRAM GND 1.225V Reference RSTSENSE RSTVDD SENSE V DD TPS3807 TIMING DIAGRAM V GOOD V ON 0.8V 0V V DD RSTSENSE RSTVDD Time V LOW V OFF t D = Reset Delay = Undefined State TPS3807 SBVS061B – AUGUST 2005 – REVISED DECEMBER 2006 Table 1. PIN DESCRIPTIONS NAME PIN NO. I/O DESCRIPTION RSTSENSE is an open-drain output that is driven to a low-impedance state when the SENSE input is lower than the threshold voltage VSENSE IT–. RSTSENSE will remain low until RSTSENSE 1 O SENSE is above VSENSE IT+. A pull-up resistor from 10kΩ to 1MΩ should be used on this pin, and allows the reset pin to attain voltages higher than VDD. GND 2 I Ground RSTVDD is an open-drain output that is driven to a low-impedance state when the VDD input is lower than the threshold voltage VDD IT–. RSTVDD will remain low until VDD is above RSTVDD 3 O VDD IT+. A pull-up resistor from 10kΩ to 1MΩ should be used on this pin, and allows the reset pin to attain voltages higher than VDD. Supply voltage for the device and sense input for fixed-threshold RSTVDD outputs. A 0.1 µF VDD 4 I ceramic capacitor should be placed close to this pin for best VIT stability. Sense input for the adjustable-threshold RSTSENSE outputs. A resistor divider from the SENSE 5 I sense voltage can be attached to this pin to set the thresholds to the desired voltages. A 0.1 µF ceramic capacitor should be placed close to this pin for best V IT stability. Figure 1. TPS3807 Timing Diagram Showing Reset Timing (SENSE resistor divider set to 3.6V) 4 Submit Documentation Feedback |
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