TPS659110, TPS659112, TPS659113

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SWCS067B – AUGUST 2011 – REVISED NOVEMBER 2011

Power Management Unit with DCDC Controller

Check for Samples: TPS659110, TPS659112, TPS659113

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FEATURES

power initialization reset (PWRDN) for thermal

reset input

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The purpose of the TPS659110 device is to

provide the following resources:

•

32-kHz clock and reset (NRESPWRON) for

system and an additional output for reset

•

Embedded power controller (EPC) with

signal

EEPROM programmability

•

Watchdog

•

Two efficient step-down DCDC converters for

•

Two ON/OFF LED pulse generators and one

processor cores (VDD1, VDD2)

PWM generator

•

One efficient step-down DCDC converter for

•

Two comparators for system control,

I/O power (VIO)

connected to VCCS pin

•

One controller for external FETs (VDDCtrl)

•

•

Dynamic voltage scaling for processor cores

accessible in functional mode (test purpose)

•

Eight LDO voltage regulators and one RTC

LDO (supply for internal RTC)

APPLICATIONS

•

•

Portable and handheld systems

•

Two independent enable signals for

DESCRIPTION

controlling power resources (EN1, EN2).

The TPS659110 is an integrated Power Management

Alternatively, these pins can be used as a

IC available in 98-pin 0.65-mm pitch BGA package

and dedicated to applications powered by one Li-Ion

scaling for VDD1 and VDD2.

or Li-Ion polymer battery cell or 3-series Ni-MH cells

or a 5 V input, and which require multiple power rails.

•

Thermal shutdown protection and hot-die

The device provides three step-down converters, one

detection

controller for external FETs to support high current

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A real-time clock (RTC) resource with:

rail, eight LDOs, and is designed to be flexible PMIC

–

Oscillator for 32.768-kHz crystal or 32-kHz

for supporting different processors and applications.

built-in RC oscillator

Two of the step-down converters provide power for

–

Date, time and calendar

dual processor cores and support dynamic voltage

–

Alarm capability

power savings. The third converter provides power for

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Nine configurable GPIOs with multiplexed

the I/Os and memory in the system.

feature support:

The device includes eight general-purpose LDOs

–

Four can be used as enable for external

providing a wide range of voltage and current

resources, included into power up

capabilities. Five of the LDOs support 1.0 to 3.3 V

sequence and controlled by state-machine.

with 100-mV step and three (LDO1, LDO2, LDO4)

–

As GPI, GPIOs support logic-level detection

support 1.0 to 3.3 V with 50-mV step. All LDOs are

and can generate maskable interrupt for

wake-up.

In addition to the power resources, the device

–

Two of the GPIOs have 10 mA current sink

contains an EPC to manage the power sequencing

capability for driving LEDs.

requirements

of

systems

and

an

RTC.

Power

–

DCDCs switching synchronization through

sequencing is programmable by EEPROM.

an external 3-MHz clock.

Figure 1 shows the top-level diagram of the device.

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Two reset inputs, for cold reset (HDRST) and a

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PRODUCTION DATA information is current as of publication date.

Copyright © 2011, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.