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74AUP2G3404GN Datasheet(PDF) 10 Page - NXP Semiconductors

No. de pieza 74AUP2G3404GN
Descripción Electrónicos  Low-power buffer and inverter
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Fabricante Electrónico  NXP [NXP Semiconductors]
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74AUP2G3404GN Datasheet(HTML) 10 Page - NXP Semiconductors

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74AUP2G3404
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 August 2012
10 of 19
NXP Semiconductors
74AUP2G3404
Low-power buffer and inverter
[1]
For measuring enable and disable times, RL = 5 k. For measuring propagation delays, set-up and hold times, and pulse width,
RL =1M.
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8.
Test circuit for measuring switching times
001aac521
DUT
RT
VI
VO
VEXT
VCC
RL
5 k
Ω
CL
G
Table 11.
Test data
Supply voltage
Load
VEXT
VCC
CL
RL[1]
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF
5 k
 or 1 M
open
GND
2
 V
CC


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