Technical Note

5/25

BU1852GUW, BU1852GXW

www.rohm.com

2012.08 - Rev.B

© 2012 ROHM Co., Ltd. All rights reserved.

5.

Startup sequence

Fig.3 Start Sequence timing

VDD=1.8V, VDDIO=1.8V, Topr=25℃, TW=VSS

Parameter

Symbol

Limits

Unit

Conditions

Min.

Typ.

Max.

VDD Stable Time

-

-

5

ms

VDD and VDDIO are ON

at the same time.

Reset Wait Time

0

-

-

µs

1

Reset Valid Time

10

-

-

µs

I

10

-

-

µs

※

1 Even if XRST port is not used, it operates because Power On Reset is built in.

In this case, connect XRST port with VDD on the set PCB.

Note) At VDD=0V, when SCL port is changed from 0V to 0.5V or more, SCL port pulls the current. It is same in SDA, XINT,

and ROW[7:0] ports of 3V tolerant I/O. (VDDIO=0V in case of COL[11:0] ports)

Fig.4 Port operating at VDD=0V

VDD

VDDIO

XRST

SCL

SDA

VDD

Port

3V

Port

Pull Current

2～3ms

0.1～1mA

0V