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CXA3256R Datasheet(PDF) 6 Page - Sony Corporation |
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CXA3256R Datasheet(HTML) 6 Page - Sony Corporation |
6 / 23 page – 6 – CXA3256R Pin No. 15 CLK/T Clock input. 46 RESETN/T TTL TTL Vcc or GND Reset signal input. When left open, this pin goes to high level. When set to low level, the built-in CLK frequency divider circuit can be reset. 44 INV Data output polarity inversion input. When left open, this input goes to high level. (See Table 1. I/O Correspondence Table.) 45 SELECT1 Data output mode selection. (See Table 2. Operation Mode Table.) Symbol Standard voltage level Equivalent circuit Description 15 46 DVCC1 DGND1 DVEE3 44 45 or , 1.5V I I I I/O Clock input. CLK/E complementary input. When left open, this pin goes to the threshold voltage. Only CLK/E can be used for operation, but complementary inputs are recommended to attain fast and stable operation. Reset signal input. When set to low level, the built-in CLK frequency divider circuit can be reset. RESETN/E complementary input. When left open, this pin goes to the threshold voltage. Only RESETN/E can be used for operation. ECL/ PECL TTL 13 14 48 47 CLK/E CLKN/E RESETN/E RESET/E I Power saving. When left open, this pin goes to high level. When set to low level, the power saving state is established. 18 PS I I I I 13 14 48 47 DGND3 DVEE3 DVCC1 DGND1 18 |
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Descripción similar - CXA3256R |
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