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CXD3029R Datasheet(PDF) 62 Page - Sony Corporation

No. de pieza CXD3029R
Descripción Electrónicos  CD Digital Signal Processor with Built-in Digital Servo Shock-proof Memory Controller Digital High & Bass Boost
Download  201 Pages
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Fabricante Electrónico  SONY [Sony Corporation]
Página de inicio  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXD3029R Datasheet(HTML) 62 Page - Sony Corporation

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CXD3029R
MSL2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
The entire DRAM area can be used as audio data.
32K bits
64K bits
128K bits
256K bits
512K bits
1M bits
2M bits
MSL1
MSL0
DRAM area that can be accessed from the microcomputer
∗: preset
REF SEL:
This bit sets the DRAM refresh rate. (Use this bit in conjunction with the $AC command
REFSEL2.)
REF ON:
This bit sets the DRAM refresh function on/off.
When "0", the refresh function is off. (default)
When "1", the refresh function is on.
XOE OUT:
This bit switches the WFCK pin output mode.
When “0”, WFCK is output from the WFCK pin. (default)
When “1”, XOE is output from the WFCK pin.
MSL2 to MSL0: These bits set the DRAM area that can be accessed from the microcomputer.
REFSEL2
0
0
1
1
0
1
0
1
11.51ms/2048 times
5.81ms/2048 times
46.44ms/2048 times
23.22ms/2048 times
REFSEL1
Refresh rate
∗: preset
ADDRST SEL: This bit selects the address reset mode.
When "0", the conventional address reset is used. (default)
When "1", the address is reset by the ADDRST command.
ADRMO:
This bit selects the remaining valid addresses.
When "0", the conventional remaining valid addresses are displayed. (default)
When "1", the remaining addresses from 0000000 to 1111111 are displayed.
GRSCOR MOD: This bit selects the GRSCOR mode.
When "0", the conventional 64-frame GRSCOR is output. (default)
XWIH2:
The XWIH condition addition is selected.
When “0”, the condition is added. (default)
When “1”, the write speed condition is added to the write prohibited condition.
XWIH1:
The XWIH condition addition is selected.
When “0”, the condition is not added. (default)
When “1”, the condition of failure access to DRAM is added to the write prohibited condition.


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