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AM3352ZCZ60 Datasheet(PDF) 1 Page - Texas Instruments

No. de pieza AM3352ZCZ60
Descripción Electrónicos  AM335x ARM Cortex-A8 Microprocessors (MPUs)
Download  222 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

AM3352ZCZ60 Datasheet(HTML) 1 Page - Texas Instruments

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AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com
SPRS717D – OCTOBER 2011 – REVISED MAY 2012
AM335x ARM® Cortex™-A8 Microprocessors (MPUs)
Check for Samples: AM3359, AM3358
1
Device Summary
1.1
Features
1234567
– 32KB of L1 Instruction Cache with Single-
• Highlights
Error Detection (parity)
– 275-MHz, 500-MHz, 600-MHz, or 720-MHz
– 32KB of L1 Data Cache with Single Error-
ARM® Cortex™-A8 32-Bit RISC
Detection (parity)
Microprocessor
– 256KB of L2 Cache with Error Correcting
NEON™ SIMD Coprocessor
Code (ECC)
32KB/32KB of L1 Instruction/Data Cache
– 176KB of On-Chip Boot ROM
with Single-Error Detection (parity)
– 64KB of Dedicated RAM
256KB of L2 Cache with Error Correcting
Code (ECC)
– Emulation/Debug
– mDDR(LPDDR)/DDR2/DDR3 Support
JTAG
– General-Purpose Memory Support (NAND,
Embedded Trace Module
NOR, SRAM, etc.) Supporting Up to 16-bit
Embedded Trace Buffer
ECC
– Interrupt Controller (up to 128 interrupt
– SGX530 3D Graphics Engine
requests)
– LCD and Touchscreen Controller
• On-Chip Memory (Shared L3 RAM)
– Programmable Real-Time Unit and Industrial
– 64 KB of General-Purpose On-Chip Memory
Communication Subsystem (PRU-ICSS)
Controller (OCMC) RAM
– Real-Time Clock (RTC)
– Accessible to all Masters
– Up to Two USB 2.0 High-Speed OTG Ports
– Supports Retention for Fast Wake-Up
with Integrated PHY
• External Memory Interfaces (EMIF)
– 10/100/1000 Ethernet Switch Supporting Up
– mDDR/DDR2/DDR3 Controller:
to Two Ports
mDDR: 200-MHz Clock (400-MHz Data
– Serial Interfaces Including:
Rate)
Two Controller Area Network Ports (CAN)
DDR2: 266-MHz Clock (532-MHz Data
Six UARTs, Two McASPs, Two McSPI,
Rate)
and Three I2C Ports
DDR3: 303-MHz-MHz Clock (606-MHz Data
– 12-Bit Successive Approximation Register
Rate)
(SAR) ADC
16-Bit Data Bus
– Up to Three 32-Bit Enhanced Capture
1 GB of Total Addressable Space
Modules (eCAP)
Supports One x16 or Two x8 Memory
– Up to Three Enhanced High-Resolution PWM
Device Configurations
Modules (eHRPWM)
Supports Retention for Fast Wake-Up
– Crypto Hardware Accelerators (AES, SHA,
– General-Purpose Memory Controller (GPMC)
PKA, RNG)
Flexible 8/16-Bit Asynchronous Memory
Interface with Up to seven Chip Selects
• MPU Subsystem
(NAND, NOR, Muxed-NOR, SRAM, etc.)
– 275-MHz, 500-MHz, 600-MHz, or 720-MHz
Uses BCH Code to Support 4-Bit, 8-Bit, or
ARM® Cortex™-A8 32-Bit RISC
16-Bit ECC
Microprocessor
Uses Hamming Code to Support 1-Bit
– NEON™ SIMD Coprocessor
ECC
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
SmartReflex, DSP/BIOS, XDS are trademarks of Texas Instruments.
3
Cortex, NEON are trademarks of ARM Ltd or its subsidiaries.
4
ARM is a registered trademark of ARM Ltd or its subsidiaries.
5
EtherCAT is a registered trademark of EtherCAT Technology Group.
6
POWERVR SGX is a trademark of Imagination Technologies Limited.
7
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative or design phase of
Copyright © 2011–2012, Texas Instruments Incorporated
development. Characteristic data and other specifications are design goals. Texas
Instruments reserves the right to change or discontinue these products without notice.


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