TSA7887BRZ datasheet(9/20 Pages) TOUCHSTONE

No. de pieza	TSA7887BRZ

Descripción Electrónicos	A Micropower, 2-channel, 125-ksps, Serial-Output 12-bit SAR ADC

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Fabricante Electrónico	TOUCHSTONE [Touchstone Semiconductor Inc]

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TSA7887

TSA7887DS r1p0

Page 9

RTFDS

DESCRIPTION OF OPERATION

The

TSA7887

is

a

single-supply,

low-power,

single/dual-channel,

12-bit

successive-

approximation ADC

with an easy-to-use serial

interface. The ADC can be operated from a 3V

supply (2.7V to 3.6V) or from a 5V supply (4.75V to

5.25V). When operated from either a 3V or 5V

supply, the TSA7887 can operate at throughput

rates up to 125ksps when an external 2 MHz clock is

applied.

In 8-pin SOIC and MSOP packages, the TSA7887

integrates

a

2.5-V

reference,

a

high-speed

track/hold, a successive-approximation ADC, and a

serial digital interface. An external serial clock is

used to transfer data to/from the ADC and controls

the TSA7887’s conversion process. The TSA7887

can

be

configured

for

single-

or

two-channel

operation. When configured as a single-channel

ADC, the analog input range is 0 to VREF (where an

externally applied VREF, if used, can range between

1.2 V and VDD). When the TSA7887 is configured

for two-channel applications, the analog input range

on each channel is set internally from 0V to VDD.

If the TSA7887 is configured for single-channel

operation, the TSA7887 can be operated in a read-

only mode by applying a logic LOW at all times to

the DIN pin (Pin 6) or by hard-wiring the DIN pin

permanently to GND. For maximum flexibility to

address

multiple

configurations

based

on

the

application, the DIN input can be used to load ADC

configuration data from a host processor into the

TSA7887’s 8-bit Control Register.

TSA7887 Operation and Transfer Function

The TSA7887 is a successive-approximation ADC,

the core of which is a charge-redistribution DAC.

Figure 1 illustrates an equivalent circuit for the

TSA7887 in signal acquisition phase. Here, Switch

SW1 is in Position A and Switch SW2 is closed. With

the sampling capacitor’s terminals connected to the

analog input on one side and REF on the other, the

analog signal is acquired. During the acquisition

phase, the inputs to the comparator are balanced

since both inputs are connected to REF.

During the conversion phase as shown in the

equivalent circuit in Figure 2, Switch SW1 is moved

from Position A to GND at Position B and Switch

SW2 is opened. At this point in time, the inputs to

the

comparator

become

unbalanced.

The

TSA7887’s

control

logic

and

the

charge-

redistribution DAC work together to add or subtract

fixed packets of charge from the sampling capacitor

to

balance

once

again

the

comparator

input

terminals. At the time when the comparator is

rebalanced, the conversion process is complete and

the ADC’s control logic generates the ADC serial

output conversion data.

Figure 3 illustrates the ideal transfer function for the

TSA7887 where the output data is coded straight

binary. Thus, the designed code transitions occur at

successive integer LSB values (that is, at 1 LSB, at

2 LSBs, etc) where the LSB size is VREF/4096.

Figure 1:

TSA7887’s Acquisition Phase Equivalent

Circuit

Figure 2: TSA7887

’s Conversion Phase Equivalent

Circuit

Figure 3:

TSA7887’s Unipolar Transfer Function for

Straight Binary Digital Data.

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TSA7887BRZ Datasheet(PDF) 9 Page - Touchstone Semiconductor Inc

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