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FM25L04B Datasheet(PDF) 7 Page - Cypress Semiconductor |
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FM25L04B Datasheet(HTML) 7 Page - Cypress Semiconductor |
7 / 14 page FM25L04B - Automotive Temp. Document Number: 001-86152 Rev. *A Page 7 of 14 Table 4. Write Protection WEL /WP Protected Blocks Unprotected Blocks Status Register 0 X Protected Protected Protected 1 0 Protected Protected Protected 1 1 Protected Unprotected Unprotected Memory Operation The SPI interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the F-RAM technology. Unlike SPI-bus EEPROMs, the FM25L04B can perform sequential writes at bus speed. No page register is needed and any number of sequential writes may be performed. Write Operation All writes to the memory array begin with a WREN op-code. The next op-code is the WRITE instruction. This op-code must include the address MSB. It is followed by a single byte address value. In total, the 9-bits specify the address of the first byte of the write operation. Subsequent bytes are data and they are written sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 1FFh is reached, the counter will roll over to 000h. Data is written MSB first. A write operation is shown in Figure 9. Unlike EEPROMs, any number of bytes can be written sequentially and each byte is written to memory immediately after it is clocked in (after the 8 th clock). The rising edge of /CS terminates a WRITE op-code operation. Asserting /WP active in the middle of a write operation will have no effect until the byte being written has completed. Read Operation After the falling edge of /CS, the bus master can issue a READ op-code. This op-code must include the address MSB. It is followed by a single byte address value. In total, the 9-bits specify the address of the first byte of the read operation. After the op-code and address are complete, the SI line is ignored. The bus master issues 8 clocks, with one bit read out for each. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 1FFh is reached, the counter will roll over to 000h. Data is read MSB first. The rising edge of /CS terminates a READ op-code operation. A read operation is shown in Figure 10. Hold The /HOLD pin can be used to interrupt a serial operation without aborting it. If the bus master pulls the /HOLD pin low while SCK is low, the current operation will pause. Taking the /HOLD pin high while SCK is low will resume an operation. The transitions of /HOLD must occur while SCK is low, but the SCK and /CS pins can toggle during a hold state. CS SCK SI SO 0 1 2 3 4 5 6 7 0 0 Hi-Z 1 MSB LSB 0 1 2 3 4 6 7 A7 0 Op-code 8-bit Address 0 A0 A3 A4 A5 A6 0 1 2 3 4 5 6 7 7 Data In 0 1 2 3 4 5 6 MSB LSB 7 0 0 0 A8 A1 A2 5 Figure 9. Memory Write (WREN not shown) CS SCK SI SO 0 1 2 3 4 5 6 7 0 0 Hi-Z 1 0 Op-code 0 1 2 3 4 5 6 7 7 Data Out 0 1 2 3 4 5 6 MSB LSB 7 0 1 0 0 A8 MSB LSB 0 1 2 3 4 6 7 A7 8-bit Address A0 A3 A4 A5 A6 A1 A2 5 Figure 10. Memory Read |
Número de pieza similar - FM25L04B |
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Descripción similar - FM25L04B |
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