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AD5532 Datasheet(PDF) 8 Page - Analog Devices

No. de pieza AD5532
Descripción Electrónicos  32-Channel, 14-Bit Voltage-Output DAC
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD5532 Datasheet(HTML) 8 Page - Analog Devices

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REV. 0
AD5532
–8–
PIN FUNCTION DESCRIPTION
Pin
Function
AGND (1–2)
Analog GND Pins.
AVCC (1–2)
Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.
VDD (1–4)
VDD Supply Pins. Voltage range from 8 V to 16.5 V.
VSS (1–4)
VSS Supply Pins. Voltage range from –4.75 V to –16.5 V.
DGND
Digital GND Pins.
DVCC
Digital Supply Pins. Voltage range from 2.7 V to 5.25 V.
DAC_GND(1–2)
Reference GND Supply for All the DACs.
REF_IN
Reference Voltage for Channels 0–31.
REF_OUT
Reference Output Voltage.
VOUT (0–31)
Analog Output Voltages from the 32 Channels.
VIN
Analog Input Voltage. Connect this to AGND if operating in DAC mode only.
A4–A1
1, A02
Parallel Interface: 5-Address Pins for 32 Channels. A4 = MSB of Channel Address. A0 = LSB.
CAL1
Parallel Interface: Control input that allows all 32 channels to acquire VIN simultaneously.
CS/SYNC
This pin is both the active low Chip Select pin for the parallel interface and the Frame Synchronization pin
for the serial interface.
WR1
Parallel Interface: Write pin. Active low. This is used in conjunction with the
CS pin to address the device
using the parallel interface.
OFFSET_SEL
1
Parallel Interface: Offset Select Pin. Active high. This is used to select the offset channel.
SCLK
2
Serial Clock Input for Serial Interface. This operates at clock speeds up to 14 MHz (20 MHz in SHA mode).
DIN
2
Data Input for Serial Interface. Data must be valid on the falling edge of SCLK.
DOUT
Output from the DAC Registers for readback. Data is clocked out on the rising edge of SCLK and is
valid on the falling edge of SCLK.
SER/
PAR1
This pin allows the user to select whether the serial or parallel interface will be used. If the pin is tied low,
the parallel interface will be used. If it is tied high, the serial interface will be used.
OFFS_IN
Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to
this pin if the user wants to drive this pin with the Offset Channel.
OFFS_OUT
Offset Output. This is the acquired/programmed offset voltage which can be tied to OFFS_IN to offset the
span.
BUSY
This output tells the user when the input voltage is being acquired. It goes low during acquisition and
returns high when the acquisition operation is complete.
TRACK/RESET2
If this input is held high, VIN is acquired once the channel is addressed. While it is held low, the input to the
gain/offset stage is switched directly to VIN. The addressed channel begins to acquire VIN on the rising edge
of
TRACK. See TRACK Input section for further information. This input can also be used as a means of
resetting the complete device to its power-on-reset conditions. This is achieved by applying a low-going
pulse of between 50 ns and 150 ns to this pin. See section on
RESET Function for further details.
NOTES
1Internal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition.
2Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition.
2.96 3V
70mV
0V
VOUT
IDEAL
TRANSFER
FUNCTION
ACTUAL
TRANSFER
FUNCTION
OFFSET
ERROR
GAIN ERROR +
OFFSET ERROR
VIN
UPPER
DEADBAND
LOWER
DEADBAND
Figure 7. SHA Transfer Function
IDEAL TRANSFER
FUNCTION
IDEAL GAIN
REFIN
DAC CODE
OUTPUT
VOLTAGE
IDEAL GAIN
50mV
0
16k
FULL-SCALE
ERROR RANGE
OFFSET
RANGE
Figure 6. DAC Transfer Function (OFFS_IN = 0)


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