AD570

REV. A

–5–

ZERO OFFSET

The apparent zero point of the AD570 can be adjusted by in-

serting an offset voltage between the analog common of the de-

vice and the actual signal return or signal common. Figure 7

illustrates two methods of providing this offset. Figure 7a shows

how the converter zero may be offset by up to

±3 bits to correct

the device initial offset and/or input signal offsets. As shown, the

circuit gives approximately symmetrical adjustment in unipolar

mode. In bipolar mode R2 should be omitted to obtain a sym-

metrical range.

Figure 7a.

Figure 7b.

Figure 8 shows the nominal transfer curve near zero for an

AD570 in unipolar mode. The code transitions are at the edges

of the nominal bit weights. In some applications it will be pref-

erable to offset the code transitions so that they fall between the

nominal bit weights, as shown in the offset characteristics. This

offset can easily be accomplished as shown in Figure 7b.

At balance (after a conversion) approximately 2 mA flows into

the analog common terminal. A 10

Ω resistor in series with this

terminal will result in approximately the desired 1/2 bit offset of

the transfer characteristics. The nominal 2 mA analog common

current is not closely controlled in manufacture. If high accuracy

is required, a 20

Ω potentiometer (connected as a rheostat) can

be used as R1. Additional negative offset range may be obtained

by using larger values of R1. Of course, if the zero transition

point is changed, the full-scale transition point will also move.

Thus, if an offset of 1/2 LSB is introduced, full-scale trimming

as described on previous page should be done with an analog

input of 9.941 volts.

Figure 8. AD570 Transfer Curve—Unipolar Operation

(Approximate Bit Weights Shown for Illustration, Nominal

Bit Weights

36.1 mV)

NOTE: During a conversion transient currents from the analog

common terminal will disturb the offset voltage. Capacitive de-

coupling should not be used around the offset network. These

transients will settle as appropriate during a conversion. Capaci-

tive decoupling will “pump up” and fail to settle resulting in

conversion errors. Power supply decoupling which returns to

analog signal common should go to the signal input side of the

resistive offset network.

CONTROL AND TIMING OF THE AD570

There are several important timing and control features on the

AD570 which must be understood precisely to allow optimal

interfacing to microprocessor or other types of control systems.

All of these features are shown in the timing diagram in Figure 9.

The normal standby situation is shown at the left end of the

drawing. The BLANK and CONVERT (B & C) line is held

high, the output lines will be “open”, and the DATA READY

(DR) line will be high. This mode is the lowest power state of

the device (typically 150 mW). When the (B & C ) line is

brought low, the conversion cycle is initiated; but the DR and

data lines do not change state. When the conversion cycle is

complete (typically 25

µs), the DR line goes low, and within

500 ns, the data lines become active with the new data.

About 1.5

µs after the B & C line is again brought high, the DR

line will go high and the data lines will go open. When the

B & C line is again brought low, a new conversion will begin.

The minimum pulse width for the B & C line to blank previous

data and start a new conversion is 2

µs. If the B & C line is

brought high during a conversion, the conversion will stop, and