AD660 TO MC68HC11 (SPI BUS) INTERFACE

The AD660 interface to the Motorola SPI (serial peripheral in-

terface) is shown in Figure 8. The MOSI, SCK, and SS pins of

the HC11 are respectively connected to the BIT0, CS and

LDAC pins of the AD660. The SER pin of the AD660 is tied

low causing the first rank latch to be transparent. The majority

of the interfacing issues are taken care of in the software initial-

ization. A typical routine such as the one shown below begins by

initializing the state of the various SPI data and control registers.

The most significant data byte (MSBY) is then retrieved from

memory and processed by the SENDAT subroutine. The SS

pin is driven low by indexing into the PORTD data register and

clear Bit 5. This causes the 2nd rank latch of the AD660 to be-

come transparent. The MSBY is then set to the SPI data regis-

ter where it is automatically transferred to the AD660.

The HC11 generates the requisite 8 clock pulses with data valid

on the rising edges. After the most significant byte is transmit-

ted, the least significant byte (LSBY) is loaded from memory

and transmitted in a similar fashion. To complete the transfer,

the LDAC pin is driven high latching the complete 16-bit word

into the AD660.

INIT

LDAA

#$2F

;SS = I; SCK = 0; MOSI = I

STAA

PORTD

;SEND TO SPI OUTPUTS

LDAA

#$38

;SS, SCK,MOSI = OUTPUTS

STAA

DDRD

;SEND DATA DIRECTION INFO

LDAA

#$50

;DABL INTRPTS,SPI IS MASTER & ON

STAA

SPCR

;CPOL=0, CPHA = 0,1MHZ BAUD RATE

NEXTPT

LDAA

MSBY

;LOAD ACCUM W/UPPER 8 BITS

BSR

SENDAT

;JUMP TO DAC OUTPUT ROUTINE

JMP

NEXTPT

;INFINITE LOOP

SENDAT

LDY

#$1000

;POINT AT ON-CHIP REGISTERS

BCLR

$08,Y,$20

;DRIVE SS (LDAC) LOW

STAA

SPDR

;SEND MS-BYTE TO SPI DATA REG

WAIT1

LDAA

SPSR

;CHECK STATUS OF SPIE

BPL

WAIT1

;POLL FOR END OF X-MISSION

LDAA

LSBY

;GET LOW 8 BITS FROM MEMORY

STAA

SPDR

;SEND LS-BYTE TO SPI DATA REG

WAIT2

LDAA

SPSR

;CHECK STATUS OF SPIE

BPL

WAIT2

;POLL FOR END OF X-MISSION

BSET

$08,Y,$20

;DRIV SS HIGH TO LATCH DATA

RTS

BIT0

LDAC

SER

AD660

MDSI

SCK

68HC11

CS

SS

Figure 8. AD660 to 68HC11 (SPI) Interface

AD660 TO MICROWIRE INTERFACE

The flexible serial interface of the AD660 is also compatible

with the National Semiconductor MICROWIRE

™ interface.

The MICROWIRE interface is used on microcontrollers such as

the COP400 and COP800 series of processors. A generic inter-

face to the MICROWIRE interface is shown in Figure 9. The

G1, SK, And SO pins of the MICROWIRE interface are respec-

tively connected to the LDAC, CS and BIT0 pins of the

AD660.

MICROWIRE is a registered trademark of National Semiconductor.

BIT0

LDAC

SER

AD660

SO

SK

MICROWIRE

™

CS

G1

Figure 9. AD660 to MICROWIRE Interface

AD660 TO ADSP-210x FAMILY INTERFACE

The serial mode of the AD660 minimizes the number of control

and data lines required to interface to digital signal processors

(DSPs) such as the ADSP-210x family. The application in Fig-

ure 10 shows the interface between an ADSP-2101 and the

AD660. Both the TFS pin and the DT pins of the ADSP-2101

should be connected to the SER and BIT0 pins of the AD660,

respectively. An inverter is required between the SCLK output

and the CS input of the AD660 in order to assure that data

transmitted to the BIT0 pin is valid on the rising edge of CS.

The serial port (SPORT) of the DSP should be configured for

alternate framing mode so that TFS complies with the word-

length framing requirement of SER. Note that the INVTFS bit

in the SPORT control register should be set to invert the TFS

signal so that SER is the correct polarity. The LDAC signal,

generated by delaying the rising edge of SER with a 74HC74

flip-flop. The CS signal clocks the flip-flop resulting in a delay

of approximately one CS clock cycle.

In applications such as waveform generation, accurate timing of

the output samples is important to avoid noise that would be in-

duced by jitter on the LDAC signal. In this example, the

ADSP-2101 is set up to use the internal timer to interrupt the

processor at the precise and desired sample rate. When the

timer interrupt occurs, the processors’s 16-bit data word is writ-

ten to the transmit register (TXn). This causes the DSP to auto-

matically generate the TFS signal and begin transmission of the

data.

BIT0

LDAC

AD660

DT

SCLK

ADSP-210x

CS

TFS

SER

D

Q

74HC04

74HC74

Figure 10. AD660 to ADSP-210x Interface

AD660 TO Z80 INTERFACE

Figure 11 shows a Zilog Z-80 8-bit microprocessor connected to

the AD660 using the byte mode interface. The double-buffered

capability of the AD660 allows the microprocessor to indepen-

dently write to the low and high byte registers, and update the

DAC output. Processor speeds up to 6 MHz on Z-80B require

no extra wait states to interface with the AD660 using a

74ALS138 as the address decoder.

AD660–Microprocessor Interface Section

–10–

REV. A