AD73311ARS datasheet(11/36 Pages) AD

No. de pieza	AD73311ARS

Descripción Electrónicos	Low Cost, Low Power CMOS General Purpose Analog Front End

Download	36 Pages

Scroll/Zoom	100%

Fabricante Electrónico	AD [Analog Devices]

Página de inicio	http://www.analog.com

Logo

11 / 36 page

AD73311

–11–

REV. B

TERMINOLOGY

Absolute Gain

Absolute gain is a measure of converter gain for a known signal.

Absolute gain is measured (differentially) with a 1 kHz sine

wave at 0 dBm0 for the DAC and with a 1 kHz sine wave at

0 dBm0 for the ADC. The absolute gain specification is used for

gain tracking error specification.

Crosstalk

Crosstalk is due to coupling of signals from a given channel

to an adjacent channel. It is defined as the ratio of the amplitude

of the coupled signal to the amplitude of the input signal.

Crosstalk is expressed in dB.

Gain Tracking Error

Gain tracking error measures changes in converter output for

different signal levels relative to an absolute signal level. The

absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz

for the DAC and 0 dBm0 (equal to absolute gain) at 1 kHz for

the ADC. Gain tracking error at 0 dBm0 (ADC) and 0 dBm0

(DAC) is 0 dB by definition.

Group Delay

Group Delay is defined as the derivative of radian phase with

respect to radian frequency, dø(f)/df. Group delay is a measure

of average delay of a system as a function of frequency. A linear

system with a constant group delay has a linear phase response.

The deviation of group delay from a constant indicates the

degree of nonlinear phase response of the system.

Idle Channel Noise

Idle channel noise is defined as the total signal energy measured

at the output of the device when the input is grounded (mea-

sured in the frequency range 300 Hz–3400 Hz).

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa

± nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which

neither m nor n are equal to zero. For final testing, the second

order terms include (fa + fb) and (fa – fb), while the third order

terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

Power Supply Rejection

Power supply rejection measures the susceptibility of a device to

noise on the power supply. Power supply rejection is measured

by modulating the power supply with a sine wave and measuring

the noise at the output (relative to 0 dB).

Sample Rate

The sample rate is the rate at which the ADC updates its output

register and the DAC updates its output from its input register.

It is fixed relative to the DMCLK (= DMCLK/256) and there-

fore may only be changed by changing the DMCLK.

SNR+THD

Signal-to-noise ratio plus harmonic distortion is defined to be

the ratio of the rms value of the measured input signal to the

rms sum of all other spectral components in the frequency range

300 Hz–3400 Hz, including harmonics but excluding dc.

ABBREVIATIONS

ADC

Analog-to-Digital Converter.

ALB

Analog Loop-Back.

BW

Bandwidth.

CRx

A Control Register where x is a placeholder for an

alphabetic character (A–E). There are five read/

write control registers on the AD73311—desig-

nated CRA through CRE.

CRx:n

A bit position, where n is a placeholder for a nu-

meric character (0–7), within a control register;

where x is a placeholder for an alphabetic charac-

ter (A–E). Position 7 represents the MSB and

Position 0 represents the LSB.

DAC

Digital-to-Analog Converter.

DLB

Digital Loop-Back.

DMCLK

Device (Internal) Master Clock. This is the inter-

nal master clock resulting from the external master

clock (MCLK) being divided by the on-chip mas-

ter clock divider.

FSLB

Frame Sync Loop Back—where the SDOFS of

the final device in a cascade is connected to the

RFS and TFS of the DSP and the SDIFS of

first device in the cascade. Data input and out-

put occur simultaneously. In the case of Non-

FSLB, SDOFS and SDO are connected to the

Rx Port of the DSP while SDIFS and SDI are

connected to the Tx Port.

PGA

Programmable Gain Amplifier.

SC

Switched Capacitor.

SNR

Signal-to-Noise Ratio.

SPORT

Serial Port.

THD

Total Harmonic Distortion.

VBW

Voice Bandwidth.

Número de pieza similar - AD73311ARS

Fabricante Electrónico	No. de pieza	Datasheet	Descripción Electrónicos
Analog Devices	AD73311ARS	340Kb / 36P	Low Cost, Low Power CMOS General Purpose Analog Front End REV. B
Analog Devices	AD73311ARSZ	340Kb / 36P	Low Cost, Low Power CMOS General Purpose Analog Front End REV. B

More results

Descripción similar - AD73311ARS

Fabricante Electrónico	No. de pieza	Datasheet	Descripción Electrónicos
Analog Devices	AD73311LARUZ	357Kb / 36P	Low Cost, Low Power CMOS General Purpose Analog Front End REV. A
	AD73311	340Kb / 36P	Low Cost, Low Power CMOS General Purpose Analog Front End REV. B
	AD73311L	381Kb / 36P	Low Cost, Low Power CMOS General Purpose Analog Front End REV. A
	AD73311L	382Kb / 36P	Low Cost, Low Power CMOS General Purpose Analog Front End REV. A
	AD73311ARZ-REEL	340Kb / 36P	Low Cost, Low Power CMOS General Purpose Analog Front End REV. B
	AD73311LARUZ-RL7	340Kb / 36P	Low Cost, Low Power CMOS General Purpose Analog Front End REV. B
	AD73311ARSZ	340Kb / 36P	Low Cost, Low Power CMOS General Purpose Analog Front End REV. B
	AD73322ARZ	389Kb / 43P	Low Cost, Low Power CMOS General-Purpose Dual Analog Front End REV. B
	AD73322	389Kb / 43P	Low Cost, Low Power CMOS General-Purpose Dual Analog Front End REV. B
	AD73322	386Kb / 43P	Low Cost, Low Power CMOS General-Purpose Dual Analog Front End REV. B

More results

AD73311ARS Datasheet(PDF) 11 Page - Analog Devices

AD73311ARS Datasheet(HTML) 11 Page - Analog Devices

Número de pieza similar - AD73311ARS

Descripción similar - AD73311ARS

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Descarga

Enlace URL