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AD7397 Datasheet(PDF) 4 Page - Analog Devices |
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AD7397 Datasheet(HTML) 4 Page - Analog Devices |
4 / 12 page AD7396/AD7397 –4– REV. 0 Table I. Control Logic Truth CS A/ B LDA LDB RS SHDN Input Register DAC Register L L HHHX Write to B Latched with Previous Data L HHHHX Write to A Latched with Previous Data L L H L H X Write to B B Transparent L H L H H X Write to A A Transparent H X L L H X Latched A and B Transparent H X ^ ^ H X Latched Latched with New Data from Input REG XXXXL X Reset to Zero Scale Reset to Zero Scale H XXX^ X Latched to Zero Latched to Zero ^Denotes positive edge. The SHDN pin has no effect on the digital interface data loading; however, while in the SHDN state (SHDN = 0) the output amplifiers V OUTA and VOUTB exhibit an open circuit condition. Note, the LDx inputs are level-sensitive, the respective DAC registers are in a transparent state when LDx = “0.” tCSW 1 LSB ERROR BAND tAS tAH CS A/ B tDH tDS tLS tLH tLDW tRSW tS tS LDA, LDB RS VOUT D0–D11 Figure 2. Timing Diagram B REGISTER 1 OF 12 LATCHES OF THE 2 INPUT REGISTERS TO DAC REGISTERS DBx CS A/ B RS Figure 3. Digital Control Logic |
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