–7–

REV. A

3

AD7564

PIN DESCRIPTIONS

Pin

Number

Mnemonic

Description

1

DGND

Digital Ground.

Positive power supply. This is +5 V

± 5%.

Feedback resistor for DAC C.

DAC C reference input.

Feedback resistor for DAC D.

10

DAC D reference input.

11

SDOUT

This shift register output allows multiple devices to be connected in a daisy chain configuration.

12

CLR

Asynchronous CLR input. When this input is taken low, all DAC latches are loaded with all 0s.

13

LDAC

Asynchronous LDAC input. When this input is taken low, all DAC latches are simultaneously

updated with the contents of the input latches.

14

FSIN

Level-triggered control input (active low). This is the frame synchronization signal for the input data.

When FSIN goes low, it enables the input shift register, and data is transferred on the falling edges of

CLKIN. If the address bits are valid, the 12-bit DAC data is transferred to the appropriate input

latch on the sixteenth falling edge after FSIN goes low.

15

SDIN

Serial data input. The device accepts a 16-bit word. DB0 and DB1 are DAC select bits. DB2 and

DB3 are device address bits. DB4 to DB15 contain the 12-bit data to be loaded to the selected

DAC.

16

CLKIN

Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN.

17

A1

Device address pin. This input in association with A0 gives the device an address. If DB2 and DB3

of the serial input stream do not correspond to this address, the data which follows is ignored and

not loaded to any input latch. However, it will appear at SDOUT irrespective of this.

18

A0

Device address pin. This input in association with A1 gives the device an address.

19

DAC A reference input.

20

Feedback resistor for DAC A.

21

22

23

DAC B reference input.

24

Feedback resistor for DAC B.

25

26

N/C

No Connect pin.

27

AGND

This pin connects to the back gates of the current steering switches. It should be connected to the

signal ground of the system.

28