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AD7703 Datasheet(PDF) 10 Page - Analog Devices

No. de pieza AD7703
Descripción Electrónicos  LC2MOS 20-Bit A/D Converter
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD7703 Datasheet(HTML) 10 Page - Analog Devices

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AD7703
–10–
REV. D
Initiating Calibration
Table III illustrates the calibration modes available in the
AD7703. Not shown in the table is the function of the BP/UP
pin which determines whether the converter has been calibrated
to measure bipolar or unipolar signals. A calibration step is
initiated by bringing the CAL pin high for at least 4 CLKIN
cycles and then bringing it low again. The states of SC1 and
SC2 along with the BP/UP pin will determine the type of
calibration to be performed. All three signals should be stable
before the CAL pin is taken positive. The SC1 and SC2 inputs
are latched when CAL goes high. The BP/UP input is not
latched and therefore must remain in a fixed state throughout
the calibration and measurement cycles. Any time the state of
the BP/UP is changed, a new calibration cycle must be
performed to enable the AD7703 to function properly in the
new mode.
When a calibration step is initiated, the DRDY signal will go
high and remain high until the step is finished. Table III shows
the number of clock cycles each calibration requires. Once a
calibration step is initiated it must finish before a new calibra-
tion step can be executed. In the two step system calibration
mode, the offset calibration step must be initiated before initiat-
ing the gain calibration step.
Table IV. Output Code Size After Calibration
1 LSB
CAL MODE
ZERO-SCALE
GAIN FACTOR
UNIPOLAR
BIPOLAR
Self-Cal
VAGND
VREF
(VREF –VAGND )
1048576
2(VREF –VAGND )
1048576
System Cal
SOFF
SGAIN
(SGAIN – SOFF )
1048576
2(SGAIN – SOFF )
1048576
Table III. Calibration Truth Table
CAL
SC1
SC2
CAL TYPE
ZERO-SCALE CAL FULL-SCALE CAL SEQUENCE
CALIBRATION TIME
0
0
Self-Cal
VAGND
VREF
One Step
3,145,655 Clock Cycles
1
1
System Offset
AIN
_
1st Step
1,052,599 Clock Cycles
0
1
System Gain
_
AIN
2nd Step
1,068,813 Clock Cycles
1
0
System Offset
AIN
VREF
One Step
2,117,389 Clock Cycles
NOTE
DRDY
remains high throughout the calibration sequence. In the Self-Cal mode, DRDY falls once the AD7703 has settled to the analog input. In all other modes
DRDY
falls as the device begins to settle.
When self-calibration is completed, DRDY falls and the output
port is updated with a data word that represents the analog
input signal. When a system calibration step is completed,
DRDY
will fall and the output port will be updated with the
appropriate data value (all 0s for the zero-scale point and all 1s
for the full-scale point). In the system calibration mode, the
digital filter must settle before the output code will represent the
value of the analog input signal. Tables IV and V indicate the
output code size and output coding of the AD7703 in its
various modes. In these tables, SOFF is the measured system
offset in volts and SGAIN is the measured system gain at the
full-scale point in volts.
Span and Offset Limits
Whenever a system calibration mode is used, there are limits on
the amount of offset and span which can be accommodated.
The range of input span in both the unipolar and bipolar modes
has a minimum value of 0.8 VREF and a maximum value of
2 (VREF + 0.1 V).
The amount of offset which can be accommodated depends on
whether the unipolar or bipolar mode is being used. In unipolar
mode, the system calibration modes can handle a maximum
offset of 0.2 VREF and a minimum offset of –(VREF + 0.1 V).
Thus the AD7703 in the unipolar mode can be calibrated to
mimic bipolar operation.


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