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AD7854 Datasheet(PDF) 6 Page - Analog Devices

No. de pieza AD7854
Descripción Electrónicos  3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
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AD7854 Datasheet(HTML) 6 Page - Analog Devices

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AD7854/AD7854L
–6–
REV. B
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Description
1
CONVST
Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold
mode and starts conversion. When this input is not used, it should be tied to DVDD.
2
WR
Write Input. Active low logic input. Used in conjunction with
CS and HBEN to write to internal registers.
3
RD
Read Input. Active low logic input. Used in conjunction with
CS and HBEN to read from internal
registers.
4
CS
Chip Select Input. Active low logic input. The device is selected when this input is active.
5
REFIN/
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the
REFOUT
reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this appears
at the pin. This pin can be overdriven by an external reference and can be taken as high as AVDD. When
this pin is tied to AVDD, then the CREF1 pin should also be tied to AVDD.
6AVDD
Analog Positive Supply Voltage, +3.0 V to +5.5 V.
7
AGND
Analog Ground. Ground reference for track/hold, reference and DAC.
8CREF1
Reference Capacitor (0.1
µF multilayer ceramic). This external capacitor is used as a charge source for the
internal DAC. The capacitor should be tied between the pin and AGND.
9CREF2
Reference Capacitor (0.01
µF ceramic disc). This external capacitor is used in conjunction with the on-chip
reference. The capacitor should be tied between the pin and AGND.
10
AIN(+)
Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above
AVDD at any time, and cannot go below AIN(–) when the unipolar input range is selected.
11
AIN(–)
Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above
AVDD at any time.
12
HBEN
High Byte Enable Input. The AD7854 operates in byte mode only but outputs 12 bits of data during a read
cycle with HBEN low. When HBEN is high, then the high byte of data that is written to or read from the
part is on DB0 to DB7. When HBEN is low, then the lowest byte of data being written to the part is on
DB0 to DB7. If reading from the part with HBEN low, then the lowest 12 bits of data appear on pins DB0
to DB11. This allows a single read from the ADC or from the control register in a 16-bit bus system.
However, two reads are needed to access the calibration registers. Also, two writes are necessary to write to
any of the registers.
13–21
DB0–DB8
Data Bits 0 to 8. Three state data I/O pins that are controlled by
CS, RD, WR and HBEN. Data output is
straight binary (unipolar mode) or twos complement (bipolar mode).
22
DVDD
Digital Supply Voltage, +3.0 V to +5.5 V.
23
DGND
Digital Ground. Ground reference point for digital circuitry.
24–26
DB9–DB11
Data Bits 9 to 11. Three state data output pins that are controlled by
CS, RD and HBEN. Data output is
straight binary (unipolar mode) or twos complement (bipolar mode). These output pins should be tied to
DVDD via 100 k
Ω resistors when the AD7854/AD7854L is being interfaced to an 8-bit data bus.
27
CLKIN
Master Clock Signal for the device (4 MHz for AD7854, 1.8 MHz for AD7854L). Sets the conversion and
calibration times.
28
BUSY
Busy Output. The busy output is triggered high by the falling edge of
CONVST and remains high until
conversion is completed. BUSY is also used to indicate when the AD7854/AD7854L has completed its on-
chip calibration sequence.


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