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AD7854AR Datasheet(PDF) 3 Page - Analog Devices

No. de pieza AD7854AR
Descripción Electrónicos  3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD7854AR Datasheet(HTML) 3 Page - Analog Devices

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Parameter
A Version1
B Version1
S Version1
Units
Test Conditions/Comments
POWER REQUIREMENTS
AVDD, DVDD
+3.0/+5.5
+3.0/+5.5
+3.0/+5.5
V min/max
IDD
Normal Mode
5
5.5 (1.8)
5.5 (1.8)
6 (1.8)
mA max
AVDD = DVDD = 4.5 V to 5.5 V. Typically 4.5 mA
(1.5 mA);
5.5 (1.8)
5.5 (1.8)
6 (1.8)
mA max
AVDD = DVDD = 3.0 V to 3.6 V. Typically 4.0 mA
(1.5 mA).
Sleep Mode
6
With External Clock On
10
10
10
µA typ
Full power-down. Power management bits in control
register set as PMGT1 = 1, PMGT0 = 0.
400
400
400
µA typ
Partial power-down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
With External Clock Off
5
5
5
µA max
Typically 1
µA. Full power-down. Power management
bits in control register set as PMGT1 = 1,
PMGT0 = 0.
200
200
200
µA typ
Partial power-down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
Normal Mode Power Dissipation
30 (10)
30 (10)
30 (10)
mW max
VDD = 5.5 V: Typically 25 mW (8)
20 (6.5)
20 (6.5)
20 (6.5)
mW max
VDD = 3.6 V: Typically 15 mW (5.4)
Sleep Mode Power Dissipation
With External Clock On
55
55
55
µW typ
VDD = 5.5 V
36
36
36
µW typ
VDD = 3.6 V
With External Clock Off
27.5
27.5
27.5
µW max
VDD = 5.5 V: Typically 5.5
µW
18
18
18
µW max
VDD = 3.6 V: Typically 3.6
µW
SYSTEM CALIBRATION
Offset Calibration Span
7
+0.05
× V
REF/–0.05
× V
REF
V max/min
Allowable Offset Voltage Span for Calibration
Gain Calibration Span
7
+0.025
× VREF/–0.025 × VREF
V max/min
Allowable Full-Scale Voltage Span for Calibration
NOTES
1Temperature ranges as follows: A, B Versions, –40
°C to +85°C; S Version, –55°C to +125°C.
2Specifications apply after calibration.
3Not production tested. Guaranteed by characterization at initial product release.
4Sample tested @ +25
°C to ensure compliance.
5All digital inputs @ DGND except for
CONVST @ DV
DD. No load on the digital outputs. Analog inputs @ AGND.
6CLKIN @ DGND when external clock off. All digital inputs @ DGND except for
CONVST @ DV
DD. No load on the digital outputs. Analog inputs @ AGND.
7The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7854/AD7854L can calibrate. Note also that these are voltage spans
and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)
± 0.05 × V
REF,
and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be VREF
± 0.025 × V
REF
(unipolar mode) and VREF/2
± 0.025 × V
REF (bipolar mode)). This is explained in more detail in the calibration section of the data sheet.
Specifications subject to change without notice.
REV. B
–3–
AD7854/AD7854L


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