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AD7864 Datasheet(PDF) 6 Page - Analog Devices

No. de Pieza. AD7864
Descripción  4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC
Descarga  19 Pages
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Fabricante  AD [Analog Devices]
Página de inicio  http://www.analog.com
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AD7864 Datasheet(HTML) 6 Page - Analog Devices

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AD7864
–6–
REV. A
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Description
1
BUSY
Busy Output. The busy output is triggered high by the rising edge of
CONVST and remains high until
conversion is completed on all selected channels.
2
FRSTDATA
First Data Output. FRSTDATA is a logic output which, when high, indicates that the Output Data
Register Pointer is addressing Register 1—See Accessing the Output Data Registers.
3
CONVST
Convert Start Input. Logic Input. A low-to-high transition on this input puts all track/holds into their
hold mode and starts conversion on the selected channels. In addition, the state of the Channel Sequence
Selection is also latched on the rising edge of
CONVST.
4
CS
Chip Select Input. Active Low Logic Input. The device is selected when this input is active.
5
RD
Read Input. Active Low Logic Input that is used in conjunction with
CS low to enable the data out-
puts. Ensure the
WR pin is at logic high while performing a read operation.
6
WR
Write Input. A rising edge on the
WR input, with CS low and RD high, latches the logic state on DB0
to DB3 into the channel select register.
7–10
SL1–SL4
Hardware Channel Select. Conversion sequence selection can also be made via the SL1–SL4 pins if
H/S SEL is logic zero. The selection is latched on the rising edge of CONVST. See Selecting a Conver-
sion Sequence.
11
H/S SEL
Hardware/Software Select Input. When this pin is at a Logic 0, the AD7864 conversion sequence selec-
tion is controlled via the SL1–SL4 input pins. When this pin is at Logic 1, the sequence is controlled
via the channel select register. See Selecting a Conversion Sequence.
12
AGND
Analog Ground. General Analog Ground. This AGND pin should be connected to the system’s
AGND plane.
13–16
VIN4X, VIN3X
Analog Inputs. See Analog Input section.
17
AGND
Analog Ground. Analog Ground reference for the attenuator circuitry. This AGND pin should be
connected to the system’s AGND plane.
18–21
VIN2X, VIN1X
Analog Inputs. See Analog Input section.
22
STBY
Standby Mode Input. TTL-compatible input that is used to put the device into the power save or
standby mode. The
STBY input is high for normal operation and low for standby operation.
23
VREF GND
Reference Ground. Ground reference for the part’s on-chip reference buffer. The VREF GND pin
should be connected to the system’s AGND plane.
24
VREF
Reference Input/Output. This pin provides access to the internal reference (2.5 V
± 5%) and also
allows the internal reference to be overdriven by an external reference source (2.5 V). A 0.1
µF decou-
pling capacitor should be connected between this pin and AGND.
25
AVDD
Analog Positive Supply Voltage, +5.0 V
± 5%.
26
AGND
Analog Ground. Analog Ground reference for the DAC circuitry.
27
INT/EXT CLK
Internal/External Clock Select Input. When this pin is at a Logic 0, the AD7864 uses its internally
generated master clock. When this pin is at Logic 1, the master clock is generated externally to the
device.
28
CLKIN
Conversion Clock Input. This is an externally applied clock that allows the user to control the conver-
sion rate of the AD7864. Each conversion needs fourteen clock cycles in order for the conversion to be
completed and an
EOC pulse to be generated. The clock should have a duty cycle that is no worse than
60/40. See Using an External Clock.
29–34
DB11–DB6
Data Bit 11 is the MSB, followed by Data Bit 10 to Data Bit 6. Three-state TTL outputs. Output
coding is 2s complement for the AD7864-1 and AD7864-3. Output coding is straight (natural) binary
for the AD7864-2.
35
DVDD
Positive supply voltage for digital section, +5.0 V
± 5%. A 0.1 µF decoupling capacitor should be con-
nected between this pin and AGND. Both DVDD and AVDD should be externally tied together.
36
VDRIVE
This pin provides the positive supply voltage for the output drivers (DB0 to DB11), BUSY,
EOC and
FRSTDATA. It is normally tied to DVDD. VDRIVE should be decoupled with a 0.1 µF capacitor. It allows
improved performance when reading during the conversion sequence. To facilitate interfacing to 3 V proces-
sors and DSPs the output data drivers may also be powered by a 3 V
± 10% supply .
37
DGND
Digital Ground. Ground reference for digital circuitry. This DGND pin should be connected to the
system’s AGND plane at the AGND pin.
38, 39
DB5, DB4
Data Bit 5 to Data Bit 4. Three-state TTL Outputs.
40–43
DB3–DB0
Data Bit 3 to Data Bit 0. Bidirectional Data Pins. When a read operation takes place, these pins are three-
state TTL outputs. The channel select register is programmed with the data on the DB0–DB3 pins with
standard
CS and WR signals. DB0 represents Channel 1 and DB3 which represents Channel 4.
44
EOC
End-of-Conversion. Active low logic output indicating conversion status. The end of each conversion in
a conversion sequence is indicated by a low-going pulse on this line.


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