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AD7864 Datasheet(PDF) 8 Page - Analog Devices |
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AD7864 Datasheet(HTML) 8 Page - Analog Devices |
8 / 19 page AD7864 –8– REV. A CONVERTER DETAILS The AD7864 is a high speed, low power, 4-channel simulta- neous sampling 12-bit A/D converter that operates from a single +5 V supply. The part contains a 1.65 µs successive approxima- tion ADC, four track/hold amplifiers, an internal +2.5 V refer- ence and a high speed parallel interface. There are four analog inputs that can be simultaneously sampled thus preserving the relative phase information of the signals on all four analog in- puts. Thereafter, conversions will be completed on the selected subset of the four channels. The part accepts an analog input range of ±10 V or ±5 V (AD7864-1), ±2.5 V (AD7864-3) and 0 V–2.5 V or 0 V–5 V (AD7864-2). Overvoltage protection on the analog inputs of the part allows the input voltage to go to ±20 V, (AD7864-1 ±10 V range), –7 V or +20 V (AD7864-1 ±5 V range) –1 V to +20 V (AD7864-2) and –7 V to +20 V (AD7864-3) without causing damage or effecting a conversion in progress. The AD7864 has two operating modes Reading Between Conversions and Reading after the Conversion Sequence. These modes are discussed in more detail in the Timing and Control section. A conversion is initiated on the AD7864 by pulsing the CONVST input. On the rising edge of CONVST, all four on-chip track/ holds are placed into hold simultaneously and the conversion sequence is started on all the selected channels. Channel selection is made via the SL1–SL4 pins if H/S SEL is logic zero or via the channel select register if H/S SEL is logic one—see Selecting a Conversion Sequence. The channel select register is programmed via the bidirectional data lines DB0–DB3 and a standard write operation. The selected conversion sequence is latched on the rising edge of CONVST so changing a selection will only take effect once a new conversion sequence is initiated. The BUSY output signal is triggered high on the rising edge of CONVST and will remain high for the duration of the conver- sion sequence. The conversion clock for the part is generated internally using a laser-trimmed clock oscillator circuit. There is also the option of using an external clock, by tying the INT/ EXT CLK pin logic high, and applying an external clock to the CLKIN pin. However, the optimum throughput is obtained by using the internally generated clock—see Using an External Clock. The EOC signal indicates the end of each conversion in the conversion sequence. The BUSY signal indicates the end of the full conversion sequence and at this time all four Track and Holds return to tracking mode. The conversion results can either be read at the end of the full conversion sequence (indicated by BUSY going low) or as each result becomes available (indicated by EOC going low). Data is read from the part via a 12-bit parallel data bus with standard CS and RD signals—see Timing and Control. Conversion time for each channel of the AD7864 is 1.65 µs and the track/hold acquisition time is 0.35 µs. To obtain optimum performance from the part, the read operation should not occur during a channel conversion or during the 100 ns prior to the next CONVST rising edge. This allows the part to operate at throughput rates up to 130 kHz for all four channels and achieve data sheet specifications. Track/Hold Section The track/hold amplifiers on the AD7864 allows the ADCs to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. The input bandwidth of the track/hold is greater than the Nyquist rate of the ADC even when the ADC is oper- ated at its maximum throughput rate of 500 kSPS (i.e., the track/hold can handle input frequencies in excess of 250 kHz). The track/hold amplifiers acquire input signals to 12-bit accu- racy in less than 350 ns. The operation of the track/holds are essentially transparent to the user. The four track/hold amplifi- ers sample their respective input channels simultaneously, on the rising edge of CONVST. The aperture time for the track/ holds (i.e., the delay time between the external CONVST signal and the track/hold actually going into hold) is typically 15 ns and, more importantly, is well matched across the four track/ holds on one device and also well matched from device to de- vice. This allows the relative phase information between differ- ent input channels to be accurately preserved. It also allows multiple AD7864s to sample more than four channels simulta- neously. At the end of a conversion sequence, the part returns to its tracking mode. The acquisition time of the track/hold amplifiers begin at this point. Reference Section The AD7864 contains a single reference pin, labelled VREF, which either provides access to the part’s own +2.5 V reference or to which an external +2.5 V reference can be connected to provide the reference source for the part. The part is specified with a +2.5 V reference voltage. Errors in the reference source will result in gain errors in the AD7864’s transfer function and will add to the specified full-scale errors on the part. On the AD7864-1 and AD7864-3, it will also result in an offset error injected in the attenuator stage, see Figures 2 and 4. The AD7864 contains an on-chip +2.5 V reference. To use this reference as the reference source for the AD7864, simply con- nect a 0.1 µF disc ceramic capacitor from the V REF pin to AGND. The voltage that appears at this pin is internally buffered before being applied to the ADC. If this reference is used externally to the AD7864, it should be buffered, as the part has a FET switch in series with the reference output resulting in a source imped- ance for this output of 6 k Ω nominal. The tolerance on the internal reference is ±10 mV at 25°C with a typical temperature coefficient of 25 ppm/ °C and a maximum error over tempera- ture of ±20 mV. If the application requires a reference with a tighter tolerance or the AD7864 needs to be used with a system reference, the user has the option of connecting an external reference to this VREF pin. The external reference will effectively overdrive the internal reference and thus provide the reference source for the ADC. The reference input is buffered before being applied to the ADC with the maximum input current of ±100 µA. Suitable reference sources for the AD7864 include the AD680, AD780, REF192 and REF43 precision +2.5 V references. CIRCUIT DESCRIPTION Analog Input Section The AD7864 is offered as three part types: the AD7864-1, where each input can be configured for ±10 V or a ±5 V input voltage range; the AD7864-3 which handles input voltage range ±2.5 V; the AD7864-2, where each input can be configured to have a 0 V to +2.5 V or 0 V to +5 V input voltage range. |
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