AD7868

–5–

REV. B

PIN FUNCTION DESCRIPTION

DIP Pin

Number

Mnemonic

Function

POWER SUPPLY

7 & 23

Positive Power Supply, 5 V

± 5%. Both V

10 & 22

Negative Power Supply, –5 V

± 5%. Both V

8 & 19

AGND

Analog Ground. Both AGND pins must be tied together.

6 &17

DGND

Digital Ground. Both DGND pins must be tied together.

ANALOG SIGNAL AND REFERENCE

21

ADC Analog Input. The ADC input range is

±3 V.

Analog Output Voltage from DAC. This output comes from a buffer amplifier. The range is

bipolar,

±3 V with RI DAC = +3 V.

20

RO ADC

Voltage Reference Output. The internal ADC 3 V reference is provided at this pin. This output may be

used as a reference for the DAC by connecting it to the RI DAC input. The external load capability of

this reference is 500

µA.

11

RO DAC

DAC Voltage Reference Output. This is one of two internal voltage references. To operate the DAC

with this internal reference, RO DAC should be connected to RI DAC. The external load capability of

the reference is 500

µA.

12

RI DAC

DAC Voltage Reference Input. The voltage reference for the DAC must be applied to this pin. It is

internally buffered before being applied to the DAC. The nominal reference voltage for correct

operation of the AD7868 is 3 V.

ADC INTERFACE AND CONTROL

2

CLK

Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying pin to

3

RFS

Receive Frame Synchronization, Logic Output. This is an active low open-drain output which provides

a framing pulse for serial data. An external 4.7 k

Ω pull-up resistor is required on RFS.

4

RCLK

Receive Clock, Logic Output. RCLK is the gated serial clock output which is derived from the internal

CONTROL input at DGND the RCLK output is gated off (three-stated) after serial transmission is

complete. RCLK is an open-drain output and requires an external 2 k

Ω pull-up resistor.

5

DR

Receive Data, Logic Output. This is an open-drain data output used in conjunction with RFS and

RCLK to transmit data from the ADC. Serial data is valid on the falling edge of RCLK when RFS is

low. An external 4.7 k

Ω resistor is required on the DR output.

1

CONVST

Convert Start, Logic Input. A low to high transition on this input puts the track-and-hold amplifier into

the hold mode and starts an ADC conversion. This input in asynchronous to the CLK input.

24

CONTROL

Control, Logic Input. With this pin at 0 V, the RCLK is noncontinuous. With this pin at –5 V, the

operation is not exhibited.

DAC INTERFACE AND CONTROL

14

TFS

Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for the DAC

with serial data expected after the falling edge of this signal.

15

DT

Transmit Data, Logic Input. This is the data input which is used in conjunction with TFS and TCLK

to transfer serial data to the input latch.

16

TCLK

Transmit Clock, Logic Input. Serial data bits are latched on the falling edge of TCLK when TFS is low.

13

LDAC

Load DAC, Logic Input. A new word is transferred into the DAC latch from the input latch on the

falling edge of this signal.

18

NC

No Connect.